Rajeev Balasubramonian

Citat de

	Toate	Din 2020
Referințe bibliografice	14384	5570
h-index	51	28
i10-index	99	64

1300

650

325

975

20022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202565 139 178 172 188 188 224 286 311 450 529 601 629 778 854 863 1005 1007 1035 1116 1217 1052 1030 115

Acces public

Afișați-le pe toate

22 de articole

0 articole

disponibile

indisponibile

Pe baza cerințelor privind finanțarea

Coautori

Sandhya DwarkadasWalter N. Munster Professor, Computer Science, University of VirginiaAdresă de e-mail confirmată pe virginia.edu
Alper BuyuktosunogluIBM T. J. Watson ResearchAdresă de e-mail confirmată pe us.ibm.com
Niladrish ChatterjeeNVIDIA ResearchAdresă de e-mail confirmată pe nvidia.com
Seth H PugsleyResearch Scientist, Intel LabsAdresă de e-mail confirmată pe cs.utah.edu
Aniruddha N UdipiGoogleAdresă de e-mail confirmată pe google.com
Manu AwasthiAshoka UniversityAdresă de e-mail confirmată pe ashoka.edu.in
Kshitij SudanLead, Datacenter Strategy and Planning at MetaAdresă de e-mail confirmată pe cs.utah.edu
Anirban NagSenior Researcher at Huawei ZurichAdresă de e-mail confirmată pe huawei.com
David NellansNVIDIA ResearchAdresă de e-mail confirmată pe nellans.org
Niti MadanAMD ResearchAdresă de e-mail confirmată pe cs.utah.edu
Michael L. ScottArthur Gould Yates Professor, Computer Science, Univ. of RochesterAdresă de e-mail confirmată pe cs.rochester.edu
John Paul StrachanDirector, Peter Grünberg Institute for Neuromorphic Compute Nodes; Professor RWTH AachenAdresă de e-mail confirmată pe fz-juelich.de
Meysam TaassoriUniversity of UtahAdresă de e-mail confirmată pe cs.utah.edu
Vivek SrikumarAssociate Professor, School of Computing, University of UtahAdresă de e-mail confirmată pe cs.utah.edu
R. Stanley WilliamsTexas A & M University ECE DepartmentAdresă de e-mail confirmată pe rstanleywilliams.com
Feifei LiAlibaba Group/Alibaba CloudAdresă de e-mail confirmată pe cs.utah.edu
Karthik RamaniComputer Science Researcher and Architect, AppleAdresă de e-mail confirmată pe apple.com
John CarterIBMAdresă de e-mail confirmată pe us.ibm.com
Vijayalakshmi SrinivasanIBM T.J. Watson Research CenterAdresă de e-mail confirmată pe us.ibm.com
Surya NarayananUniversity of UtahAdresă de e-mail confirmată pe cs.utah.edu

Urmăriți

Rajeev Balasubramonian

Professor, School of Computing, University of Utah

Adresă de e-mail confirmată pe cs.utah.edu - Pagina de pornire

Computer architecture memory systems cache hierarchies


Titlu Sortați după descrierea bibliografică Sortați după an Sortați după titlu	Citat de Citat de	Anul
ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars A Shafiee, A Nag, N Muralimanohar, R Balasubramonian, JP Strachan, ... Proceedings of the 43rd International Symposium on Computer Architecture, 14-26, 2016	2295	2016
CACTI 6.0: A tool to model large caches N Muralimanohar, R Balasubramonian, NP Jouppi HP Laboratories, 22-31, 2009	1313	2009
Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 N Muralimanohar, R Balasubramonian, N Jouppi Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007	836	2007
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling G Semeraro, G Magklis, R Balasubramonian, DH Albonesi, S Dwarkadas, ... Proceedings Eighth International Symposium on High Performance Computer …, 2002	575	2002
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures R Balasubramonian, D Albonesi, A Buyuktosunoglu, S Dwarkadas Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000	571	2000
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories R Balasubramonian, AB Kahng, N Muralimanohar, A Shafiee, V Srinivas ACM Transactions on Architecture and Code Optimization (TACO) 14 (2), 14, 2017	487	2017
Overcoming the challenges of crossbar resistive memory architectures C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie 2015 IEEE 21st International Symposium on High Performance Computer …, 2015	423	2015
Rethinking DRAM design and organization for energy-constrained multi-cores AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ... Proceedings of the 37th annual international symposium on Computer …, 2010	359	2010
NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ... Performance Analysis of Systems and Software (ISPASS), 2014 IEEE …, 2014	352	2014
Reducing the complexity of the register file in dynamic superscalar processors R Balasubramonian, S Dwarkadas, DH Albonesi Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International …, 2001	317	2001
Near-Data Processing: Insights from a MICRO-46 Workshop R Balasubramonian, J Chang, T Manning, JH Moreno, R Murphy, R Nair, ... Micro, IEEE 34 (4), 36-42, 2014	316	2014
Micro-pages: increasing DRAM efficiency with locality-aware data placement K Sudan, N Chatterjee, D Nellans, M Awasthi, R Balasubramonian, ... ACM SIGARCH Computer Architecture News 38 (1), 219-230, 2010	308	2010
Leveraging 3D technology for improved reliability N Madan, R Balasubramonian Proceedings of the 40th Annual IEEE/ACM International Symposium on …, 2007	292	2007
Multiple clock domain microprocessor D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ... US Patent 7,089,443, 2006	250*	2006
Multiple clock domain microprocessor D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ... US Patent 7,089,443, 2006	250*	2006
Multiple clock domain microprocessor D Albonesi, G Semeraro, G Magklis, ML Scott, R Balasubramonian, ... US Patent 7,739,537, 2010	226	2010
Efficiently prefetching complex address patterns M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ... Proceedings of the 48th International Symposium on Microarchitecture, 141-152, 2015	218	2015
Dynamically tuning processor resources with adaptive processing DH Albonesi, R Balasubramonian, SG Dropsbo, S Dwarkadas, ... Computer 36 (12), 49-58, 2003	215	2003
USIMM: the Utah SImulated Memory Module N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ... Technical report, University of Utah, 2012. UUCS-12-002, 2012	200	2012
CHOP: Adaptive filter-based dram caching for CMP server platforms X Jiang, N Madan, L Zhao, M Upton, R Iyer, S Makineni, D Newell, ... High Performance Computer Architecture (HPCA), 2010 IEEE 16th International …, 2010	199	2010

Sistemul nu poate realiza operația în acest moment. Încercați din nou mai târziu.

Articole 1–20

Referințe bibliografice pe an

Citate duplicat

Citate fuzionate

Adăugați coautoriCoautori

Urmăriți

Citat de

Coautori