| A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability SM Salahuddin, H Jiao, V Kursun International symposium on quality electronic design (ISQED), 353-358, 2013 | 60 | 2013 |
| Eight-FinFET fully differential SRAM cell with enhanced read and write voltage margins SM Salahuddin, M Chan IEEE Transactions on Electron Devices 62 (6), 2014-2021, 2015 | 38 | 2015 |
| SRAM with buried power distribution to improve write margin and performance in advanced technology nodes SM Salahuddin, KA Shaik, A Gupta, B Chava, M Gupta, P Weckx, ... IEEE electron device letters 40 (8), 1261-1264, 2019 | 35 | 2019 |
| 3D-optimized SRAM macro design and application to memory-on-logic 3D-IC at advanced nodes R Chen, P Weckx, SM Salahuddin, SW Kim, G Sisto, G Van Der Plas, ... 2020 IEEE International Electron Devices Meeting (IEDM), 15.2. 1-15.2. 4, 2020 | 30 | 2020 |
| Buried power SRAM DTCO and system-level benchmarking in N3 S Salahuddin, M Perumkunnil, ED Litta, A Gupta, P Weckx, J Ryckaert, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 26 | 2020 |
| A frequency multiplier using three ambipolar graphene transistors HMD Kabir, SM Salahuddin Microelectronics journal 70, 12-15, 2017 | 24 | 2017 |
| CFET SRAM DTCO, interconnect guideline, and benchmark for CMOS scaling HH Liu, SM Salahuddin, BT Chan, P Schuddinck, Y Xiang, G Hellings, ... IEEE Transactions on Electron Devices 70 (3), 883-890, 2023 | 21 | 2023 |
| Buried power rail metal exploration towards the 1 nm node A Gupta, D Radisic, JW Maes, OV Pedreira, JP Soulié, N Jourdan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2021 | 20 | 2021 |
| Extended methodology to determine SRAM write margin in resistance-dominated technology node HH Liu, SM Salahuddin, D Abdi, R Chen, P Weckx, P Matagne, F Catthoor IEEE Transactions on Electron Devices 69 (6), 3113-3117, 2022 | 19 | 2022 |
| DTCO of sequential and monolithic CFET SRAM HH Liu, SM Salahuddin, BT Chan, P Schuddinck, Y Xiang, P Weckx, ... DTCO and computational patterning II 12495, 218-224, 2023 | 17 | 2023 |
| Design and optimization of SRAM macro and logic using backside interconnects at 2nm node R Chen, G Sisto, A Jourdain, G Hiblot, M Stucchi, N Kakarla, B Chehab, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.4. 1-22.4. 4, 2021 | 17 | 2021 |
| CFET SRAM with double-sided interconnect design and DTCO benchmark HH Liu, P Schuddinck, Z Pei, L Verschueren, H Mertens, SM Salahuddin, ... IEEE Transactions on Electron Devices 70 (10), 5099-5106, 2023 | 14 | 2023 |
| Buried Bitline for sub-5nm SRAM Design R Mathur, M Bhargava, S Salahuddin, P Schuddinck, J Ryckaert, ... 2020 IEEE International Electron Devices Meeting (IEDM), 20.2. 1-20.2. 4, 2020 | 14 | 2020 |
| From design to system-technology optimization for CMOS J Ryckaert, B Chehab, D Jang, G Mirabelli, SM Salahuddin, P Schuddinck, ... 2021 International Symposium on VLSI Technology, Systems and Applications …, 2021 | 10 | 2021 |
| Emerging interconnect exploration for SRAM application using nonconventional H-tree and center-pin access Z Pei, M Mayahinia, HH Liu, M Tahoori, SM Salahuddin, F Catthoor, ... 2023 24th International Symposium on Quality Electronic Design (ISQED), 1-1, 2023 | 9 | 2023 |
| System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs M Perumkunnil, F Yasin, S Rao, SM Salahuddin, D Milojevic, ... 2020 IEEE International Electron Devices Meeting (IEDM), 15.4. 1-15.4. 4, 2020 | 9 | 2020 |
| Buried interconnects for sub-5 nm SRAM design R Mathur, M Bhargava, B Cline, S Salahuddin, A Gupta, P Schuddinck, ... IEEE Transactions on Electron Devices 69 (3), 1041-1047, 2022 | 8 | 2022 |
| Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap/underlap bitline access transistors for enhanced read data stability SM Salahuddin, H Jiao, V Kursun 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2331-2334, 2013 | 8 | 2013 |
| Finfet sram cells with asymmetrical bitline access transistors for enhanced read stability SM Salahuddin, V Kursun, H Jiao Transactions on Electrical and Electronic Materials 16 (6), 293-302, 2015 | 7 | 2015 |
| Thermal stress-aware CMOS–SRAM partitioning in sequential 3-D technology SM Salahuddin, ED Litta, A Gupta, R Ritzenthaler, M Schaekers, ... IEEE Transactions on Electron Devices 67 (11), 4631-4635, 2020 | 6 | 2020 |
Volkan KursunVisiting Professor, Bilkent UniversityAdresă de e-mail confirmată pe bilkent.edu.tr
