| Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors ML Lee, EA Fitzgerald, MT Bulsara, MT Currie, A Lochtefeld Journal of applied physics 97 (1), 2005 | 1329 | 2005 |
| Strained-semiconductor-on-insulator device structures TA Langdo, MT Currie, R Hammond, AJ Lochtefeld, EA Fitzgerald US Patent 6,995,430, 2006 | 539 | 2006 |
| Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same M Currie, A Lochtefeld, R Hammond, E Fitzgerald US Patent 6,831,292, 2004 | 504 | 2004 |
| Methods of forming strained-semiconductor-on-insulator finFET device structures AJ Lochtefeld, TA Langdo, R Hammond, MT Currie, G Braithwaite, ... US Patent 7,074,623, 2006 | 401 | 2006 |
| High quality Ge on Si by epitaxial necking TA Langdo, CW Leitz, MT Currie, EA Fitzgerald, A Lochtefeld, ... Applied Physics Letters 76 (25), 3700-3702, 2000 | 316 | 2000 |
| Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates using aspect ratio trapping JS Park, J Bai, M Curtin, B Adekore, M Carroll, A Lochtefeld Applied Physics Letters 90 (5), 2007 | 275 | 2007 |
| Tri-gate field-effect transistors formed by aspect ratio trapping AJ Lochtefeld US Patent 7,799,592, 2010 | 245 | 2010 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza, G Braithwaite, TA Langdo US Patent 8,324,660, 2012 | 242 | 2012 |
| On experimental determination of carrier velocity in deeply scaled NMOS: How close to the thermal limit? A Lochtefeld, DA Antoniadis IEEE Electron Device Letters 22 (2), 95-97, 2001 | 219 | 2001 |
| Shallow trench isolation process MT Currie, AJ Lochtefeld US Patent 6,960,781, 2005 | 217 | 2005 |
| Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping JZ Li, J Bai, JS Park, B Adekore, K Fox, M Carroll, A Lochtefeld, ... Applied physics letters 91 (2), 2007 | 213 | 2007 |
| Defect reduction using aspect ratio trapping J Bai, JS Park, AJ Lochtefeld US Patent 8,173,551, 2012 | 209 | 2012 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication J Li, AJ Lochtefeld US Patent 9,153,645, 2015 | 171 | 2015 |
| Lattice-mismatched semiconductor structures and related methods for device fabrication AJ Lochtefeld US Patent 7,777,250, 2010 | 167 | 2010 |
| Semiconductor sensor structures with reduced dislocation defect densities Z Cheng, JG Fiorenza, C Sheen, A Lochtefeld US Patent 8,253,211, 2012 | 157 | 2012 |
| Solutions for integrated circuit integration of alternative active area materials AJ Lochtefeld, MT Currie, ZY Cheng, J Fiorenza US Patent 7,626,246, 2009 | 155 | 2009 |
| Semiconductor devices having strained dual channel layers MT Currie, AJ Lochtefeld, CW Leitz, EA Fitzgerald US Patent 7,138,310, 2006 | 149 | 2006 |
| Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress A Lochtefeld, DA Antoniadis IEEE Electron Device Letters 22 (12), 591-593, 2001 | 146 | 2001 |
| The role of point defects and arsenic precipitates in carrier trapping and recombination in low‐temperature grown GaAs AJ Lochtefeld, MR Melloch, JCP Chang, ES Harmon Applied physics letters 69 (10), 1465-1467, 1996 | 145 | 1996 |
| Photovoltaics on silicon J Li, AJ Lochtefeld, C Sheen, Z Cheng US Patent 9,508,890, 2016 | 144 | 2016 |