A switched‐capacitor skew‐tent map implementation for random number generation JL Valtierra, E Tlelo‐Cuautle, Á Rodríguez‐Vázquez
International Journal of Circuit Theory and Applications 45 (2), 305-315, 2017
55 2017 A Sub- JL Valtierra, M Delgado-Restituto, R Fiorelli, Á Rodríguez-Vázquez
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (5), 1426-1437, 2020
21 2020 Simulation of piecewise-linear one-dimensional chaotic maps by Verilog-A JL Valtierra Sánchez de la Vega, E Tlelo-Cuautle
IETE Technical Review 32 (4), 304-310, 2015
17 2015 A sub-µW reconfigurable front-end for invasive neural recording JL Valtierra, R Fiorelli, M Delgado-Restituto, A Rodriguez-Vazquez
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 85-88, 2019
8 2019 A 32 input multiplexed channel analog front-end with spatial delta encoding technique and differential artifacts compression N Pérez-Prieto, R Fiorelli, JL Valtierra, P Pérez-García, ...
2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2019
6 2019 A Sub-μVRms Chopper Front-End for ECoG Recording N Pérez-Prieto, JL Valtierra, M Delgado-Restituto, Á Rodríguez-Vázquez
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
4 2019 A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation JL Valtierra, R Fiorelli, N Pérez-Prieto, M Delgado-Restituto, ...
2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2019
3 2019 A 2.2 μW analog front-end for multichannel neural recording JL Valtierra, M Delgado-Restituto, Á Rodríguez-Vázquez
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017
3 2017 A 4-mode reconfigurable low noise amplifier for implantable neural recording channels JL Valtierra, Á Rodríguez-Vázquez, M Delgado-Restituto
2016 12th Conference on Ph. D. Research in Microelectronics and Electronics …, 2016
2 2016 Diseño de circuitos integrados para interfaces neuronales implantables JL Valtierra Sánchez de la Vega
Universidad de Sevilla, 2020
2020 Design criteria for a discrete time chaos based CMOS true random number generator JL Valtierra Sánchez de la Vega
Instituto Nacional de Astrofísica, Óptica y Electrónica, 2014
2014 