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Dr. Chandan Kumar Pandey
Dr. Chandan Kumar Pandey
Associate Professor (School of Electronics Engineering), VIT-AP University
Подтвержден адрес электронной почты в домене vitap.ac.in
Название
Процитировано
Процитировано
Год
Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket
CK Pandey, D Dash, S Chaudhury
Micro & Nano Letters 14 (1), 86-90, 2019
622019
A review of tunnel field-effect transistors for improved ON-state behaviour
KRN Karthik, CK Pandey
Silicon 15 (1), 1-23, 2023
472023
Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances
CK Pandey, A Singh, S Chaudhury
Applied Physics A 126 (3), 225, 2020
462020
Improvement in analog/RF performances of SOI TFET using dielectric pocket
CK Pandey, D Dash, S Chaudhury
International Journal of Electronics 107 (11), 1844-1860, 2020
392020
Design and analysis of high k silicon nanotube tunnel FET device
A Singh, S Chaudhury, CK Pandey, S Madhulika Sharma, ...
IET Circuits, Devices & Systems 13 (8), 1305-1310, 2019
382019
Performance analysis of gate-stack dual-material DG MOSFET using work-function modulation technique for lower technology nodes
SK Das, U Nanda, SM Biswal, CK Pandey, LI Giri
Silicon 14 (6), 2965-2973, 2022
362022
Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction
A Singh, CK Pandey, U Nanda
Microelectronics Journal 126, 105512, 2022
322022
Impact of dielectric pocket on analog and high-frequency performances of cylindrical gate-all-around tunnel FETs
CK Pandey, D Dash, S Chaudhury
ECS Journal of Solid State Science and Technology 7 (5), N59, 2018
312018
Effect of strain in silicon nanotube FET devices for low power applications
A Singh, CK Pandey, S Chaudhury, CK Sarkar
The European Physical Journal Applied Physics 85 (1), 10101, 2019
302019
Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters
KRN Karthik, CK Pandey
ECS Journal of Solid State Science and Technology 11 (11), 2022
272022
A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET
CK Pandey, A Singh, S Chaudhury
Microelectronics Reliability 122, 114166, 2021
262021
Improved DC performances of gate-all-around si-nanotube tunnel FETs using gate-source overlap
A Singh, CK Pandey
Silicon 14 (4), 1463-1470, 2022
242022
Design and analysis of high performance multiplier circuit
I Hussain, CK Pandey, S Chaudhury
2019 Devices for Integrated Circuit (DevIC), 245-247, 2019
212019
Tuning of threshold voltage in silicon nano-tube FET using halo doping and its impact on analog/RF performances
A Singh, CK Pandey, S Chaudhury, CK Sarkar
Silicon 13 (11), 3871-3877, 2021
182021
Dual-metal graded-channel double-gate tunnel FETs for reduction of ambipolar conduction
CK Pandey, S Chaudhury
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 572-576, 2018
182018
Structural, electronic, and mechanical properties of cubic TiO2: A first-principles study
D Dash, CK Pandey, S Chaudhury, SK Tripathy
Chinese Physics B 27 (1), 017102, 2018
182018
Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET
D Das, CK Pandey
Microelectronics Reliability 146, 115024, 2023
152023
Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects
T Ashok, CK Pandey
Physica Scripta 99 (2), 025005, 2024
132024
Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET
AK Pathakamuri, CK Pandey
Physica Scripta 98 (12), 124001, 2023
132023
A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation
D Das, CK Pandey
ECS Journal of Solid State Science and Technology, 2022
112022
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