Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance DP Brunco, B De Jaeger, G Eneman, J Mitard, G Hellings, A Satta, ...
Journal of The Electrochemical Society 155 (7), H552, 2008
350 2008 Comphy—A compact-physics framework for unified modeling of BTI G Rzepa, J Franco, B O’Sullivan, A Subirats, M Simicic, G Hellings, ...
Microelectronics Reliability 85, 49-65, 2018
192 2018 Record ION /IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability J Mitard, B De Jaeger, FE Leys, G Hellings, K Martens, G Eneman, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
151 2008 Electrical TCAD simulations of a germanium pMOSFET technology G Hellings, G Eneman, R Krom, B De Jaeger, J Mitard, A De Keersgieter, ...
IEEE Transactions on Electron Devices 57 (10), 2539-2546, 2010
124 2010 Impact of Donor Concentration, Electric Field, and Temperature Effects on the Leakage Current in Germanium p G Eneman, M Wiot, A Brugere, OSI Casain, S Sonde, DP Brunco, ...
IEEE Transactions on Electron Devices 55 (9), 2287-2296, 2008
106 2008 Challenges and opportunities in advanced Ge pMOSFETs E Simoen, J Mitard, G Hellings, G Eneman, B De Jaeger, L Witters, ...
Materials Science in Semiconductor Processing 15 (6), 588-600, 2012
98 2012 Advancing CMOS beyond the Si roadmap with Ge and III/V devices M Heyns, A Alian, G Brammertz, M Caymax, YC Chang, LK Chu, ...
2011 International Electron Devices Meeting, 13.1. 1-13.1. 4, 2011
84 2011 Germanium for advanced CMOS anno 2009: A SWOT analysis M Caymax, G Eneman, F Bellenger, C Merckling, A Delabie, G Wang, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
77 2009 Impact of EOT scaling down to 0.85 nm on 70nm Ge-pFETs technology with STI J Mitard, C Shea, B DeJaeger, A Pristera, G Wang, M Houssa, G Eneman, ...
2009 Symposium on VLSI Technology, 82-83, 2009
69 2009 Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ...
2021 Symposium on VLSI Technology, 1-2, 2021
67 2021 Integration of InGaAs channel n-MOS devices on 200mm Si wafers using the aspect-ratio-trapping technique N Waldron, G Wang, ND Nguyen, T Orzali, C Merckling, G Brammertz, ...
ECS Transactions 45 (4), 115, 2012
66 2012 Scalable quantum well device and method for manufacturing the same G Hellings, G Eneman, M Meuris
US Patent 7,915,608, 2011
66 2011 High performance 70-nm germanium pMOSFETs with boron LDD implants G Hellings, J Mitard, G Eneman, B De Jaeger, DP Brunco, D Shamiryan, ...
IEEE Electron Device Letters 30 (1), 88-90, 2008
63 2008 Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS A Veloso, G Hellings, MJ Cho, E Simoen, K Devriendt, V Paraschiv, ...
2015 Symposium on VLSI Technology (VLSI Technology), T138-T139, 2015
57 2015 Ultra shallow arsenic junctions in germanium formed by millisecond laser annealing G Hellings, E Rosseel, E Simoen, D Radisic, DH Petersen, O Hansen, ...
Electrochemical and Solid-State Letters 14 (1), H39, 2010
50 2010 Single-event latch-up: Increased sensitivity from planar to FinFET J Karp, MJ Hart, P Maillard, G Hellings, D Linten
IEEE Transactions on Nuclear Science 65 (1), 217-222, 2017
47 2017 Quantification of drain extension leakage in a scaled bulk germanium PMOS technology G Eneman, B De Jaeger, E Simoen, DP Brunco, G Hellings, JÉÔ Mitard, ...
IEEE transactions on electron devices 56 (12), 3115-3122, 2009
41 2009 Implantation, diffusion, activation, and recrystallization of gallium implanted in preamorphized and crystalline germanium G Hellings, C Wuendisch, G Eneman, E Simoen, T Clarysse, M Meuris, ...
Electrochemical and Solid-State Letters 12 (12), H417, 2009
40 2009 First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ...
2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018
39 2018 Gate-all-around nanowire FETs vs. triple-gate FinFETs: on gate integrity and device characteristics A Veloso, MJ Cho, E Simoen, G Hellings, P Matagne, N Collaert, A Thean
ECS Transactions 72 (2), 85, 2016
36 2016 
Dimitri LintenImecПодтвержден адрес электронной почты в домене imec.be
