| Designing efficient circuits based on runtime-reconfigurable field-effect transistors S Rai, J Trommer, M Raitza, T Mikolajick, WM Weber, A Kumar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (3), 560-572, 2018 | 104 | 2018 |
| Reconfigurable field effect transistors: A technology enablers perspective T Mikolajick, G Galderisi, S Rai, M Simon, R Böckle, M Sistani, C Cakirlar, ... Solid-State Electronics 194, 108381, 2022 | 66 | 2022 |
| 20 Years of reconfigurable field-effect transistors: From concepts to future applications T Mikolajick, G Galderisi, M Simon, S Rai, A Kumar, A Heinzig, WM Weber, ... Solid-State Electronics 186, 108036, 2021 | 56 | 2021 |
| Logic synthesis meets machine learning: Trading exactness for generalization S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 40 | 2021 |
| Hardware watermarking using polymorphic inverter designs based on reconfigurable nanotechnologies S Rai, A Rupani, P Nath, A Kumar 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 663-669, 2019 | 38 | 2019 |
| Security promises and vulnerabilities in emerging reconfigurable nanotechnology-based circuits S Rai, S Patnaik, A Rupani, J Knechtel, O Sinanoglu, A Kumar IEEE Transactions on Emerging Topics in Computing 10 (2), 763-778, 2020 | 36 | 2020 |
| RECON: resource-efficient CORDIC-based neuron architecture G Raut, S Rai, SK Vishvakarma, A Kumar IEEE Open Journal of Circuits and Systems 2, 170-181, 2021 | 35 | 2021 |
| Emerging reconfigurable nanotechnologies: Can they support future electronics? S Rai, S Srinivasa, P Cadareanu, X Yin, XS Hu, PE Gaillardon, ... 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 35 | 2018 |
| A CORDIC based configurable activation function for ANN applications G Raut, S Rai, SK Vishvakarma, A Kumar 2020 IEEE computer society annual symposium on VLSI (ISVLSI), 78-83, 2020 | 34 | 2020 |
| A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs S Rai, A Rupani, D Walter, M Raitza, A Heinzig, T Baldauf, J Trommer, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 605-608, 2018 | 33 | 2018 |
| A versatile mapping approach for technology mapping and graph optimization AT Calvino, H Riener, S Rai, A Kumar, G De Micheli 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 410-416, 2022 | 29 | 2022 |
| Technology mapping flow for emerging reconfigurable silicon nanowire transistors S Rai, M Raitza, A Kumar 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 767-772, 2018 | 26 | 2018 |
| RL-guided runtime-constrained heuristic exploration for logic synthesis YV Peruvemba, S Rai, K Ahuja, A Kumar 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 25 | 2021 |
| Discern: Distilling standard-cells for emerging reconfigurable nanotechnologies S Rai, M Raitza, SS Sahoo, A Kumar 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 674-677, 2020 | 25 | 2020 |
| Design of energy-efficient RFET-based exact and approximate 4: 2 compressors and multipliers N Kavand, A Darjani, S Rai, A Kumar IEEE Transactions on Circuits and Systems II: Express Briefs 70 (9), 3644-3648, 2023 | 15 | 2023 |
| Germanium nanowire reconfigurable transistor model for predictive technology evaluation JN Quijada, T Baldauf, S Rai, A Heinzig, A Kumar, WM Weber, ... IEEE transactions on nanotechnology 21, 728-736, 2022 | 13 | 2022 |
| Preserving self-duality during logic synthesis for emerging reconfigurable nanotechnologies S Rai, H Riener, G De Micheli, A Kumar 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 354-359, 2021 | 12 | 2021 |
| A survey of fpga logic cell designs in the light of emerging technologies S Rai, P Nath, A Rupani, SK Vishvakarma, A Kumar IEEE Access 9, 91564-91574, 2021 | 11 | 2021 |
| Perspectives on emerging computation-in-memory paradigms S Rai, M Liu, A Gebregiorgis, D Bhattacharjee, K Chakrabarty, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 10 | 2021 |
| Logic synthesis meets machine learning: Trading exactness for generalization. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... IEEE, 1026ś1031, 2021 | 10 | 2021 |
Akash KumarFull Professor, Chair of Embedded Systems, Ruhr University BochumПодтвержден адрес электронной почты в домене rub.de
