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Zhe Wang
Zhe Wang
Texas A&M, Intel Labs；
Подтвержден адрес электронной почты в домене intel.com
Название
Процитировано
Процитировано
Год
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
Z Wang, DA Jiménez, C Xu, G Sun, Y Xie
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
1722014
Perceptron learning for reuse prediction
E Teran, Z Wang, DA Jiménez
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
1582016
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
S Khan, C Wilkerson, Z Wang, AR Alameldeen, D Lee, O Mutlu
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
1172017
Aggregated write back in a direct mapped two level memory
Z Wang, CB Wilkerson, ZA Chishti
US Patent 10,496,544, 2019
752019
WADE: Writeback-aware dynamic cache management for NVM-based main memory system
Z Wang, S Shan, T Cao, J Gu, Y Xu, S Mu, Y Xie, DA Jiménez
ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-21, 2013
592013
Improving writeback efficiency with decoupled last-write prediction
Z Wang, SM Khan, DA Jiménez
ACM SIGARCH Computer Architecture News 40 (3), 309-320, 2012
452012
Decoupled dynamic cache segmentation
SM Khan, Z Wang, DA Jiménez
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
352012
Minimal disturbance placement and promotion
E Teran, Y Tian, Z Wang, DA Jiménez
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
172016
Method and apparatus for multi-level memory early page demotion
B Pham, CB Wilkerson, AR Alameldeen, ZA Chishti, Z Wang
US Patent 10,860,244, 2020
132020
Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
Z Wang, CB Wilkerson, ZA Chishti, SH Pugsley, AR Alameldeen, SLL Lu
US Patent 10,261,901, 2019
112019
Building a low latency, highly associative dram cache with the buffered way predictor
Z Wang, DA Jiménez, T Zhang, GH Loh, Y Xie
2016 28th International Symposium on Computer Architecture and High …, 2016
112016
23.9 An 8-channel 4.5 Gb 180GB/s 18ns-row-latency RAM for the last level cache
TKJ Ting, GB Wang, MH Wang, CP Wu, CK Wang, CW Lo, LC Tien, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 404-405, 2017
92017
Method and apparatus for pre-fetching data in a system having a multi-level system memory
Z Wang, CB Wilkerson, ZA Chishti, SH Pugsley, AR Alameldeen, SLL Lu
US Patent 10,108,549, 2018
72018
Multi-level memory management
CB Wilkerson, AR Alameldeen, Z Wang, ZA Chishti
US Patent 9,583,182, 2017
72017
Rank idle time prediction driven last-level cache writeback
Z Wang, SM Khan, DA Jiménez
Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance …, 2012
72012
Multi-level memory management
CB Wilkerson, AR Alameldeen, Z Wang, ZA Chishti
US Patent 9,921,961, 2018
62018
Studying microarchitectural structures with object code reordering
SMF Rahman, Z Wang, DA Jiménez
Proceedings of the Workshop on Binary Instrumentation and Applications, 7-16, 2009
62009
一种基于立体视觉的运动目标检测算法
王哲， 常发亮
计算机应用 26 (11), 2724-2726, 2006
62006
Cache architecture using way ID to reduce near memory traffic in a two-level memory system
Z Wang, AR Alameldeen
US Patent 10,884,927, 2021
52021
Multi-level system memory with a battery backed up portion of a non volatile memory level
Z Wang, AR Alameldeen
US Patent App. 16/262,691, 2019
42019
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