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Jaan Raik
Jaan Raik
Tallinn University of Technology
Подтвержден адрес электронной почты в домене taltech.ee
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Процитировано
Процитировано
Год
Design and test technology for dependable systems-on-chip
R Ubar, J Raik, HT Vierhaus
IGI global, 2011
2032011
Fast test pattern generation for sequential circuits using decision diagram representations
J Raik, R Ubar
Journal of Electronic Testing 16, 213-226, 2000
732000
An external test approach for network-on-a-chip switches
J Raik, V Govind, R Ubar
2006 15th Asian Test Symposium, 437-442, 2006
652006
Test configurations for diagnosing faulty links in NoC switches
J Raik, R Ubar, V Govind
12th IEEE European Test Symposium (ETS'07), 29-34, 2007
582007
Parallel X-fault simulation with critical path tracing technique
R Ubar, S Devadze, J Raik, A Jutman
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
492010
Turbo Tester: a CAD system for teaching digital test
G Jervan, A Markus, P Paomets, J Raik, R Ubar
Microelectronics Education: Proceedings of the 2 nd European Workshop held …, 1998
481998
SSBDDs: Advantageous model and efficient algorithms for digital circuit modeling, simulation & test
A Jutman, J Raik, R Ubar
Proc. of 5th International Workshop on Boolean Problems (IWSBP'02), 19-20, 2002
422002
Testing strategies for networks on chip
R Ubar, J Raik
Networks on chip, 131-152, 2003
412003
Back-tracing and event-driven techniques in high-level simulation with decision diagrams
R Ubar, J Raik, A Morawiec
2000 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 208-211, 2000
372000
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips
J Raik, V Govind, R Ubar
IET computers & digital techniques 3 (5), 476-486, 2009
362009
Feasibility of structurally synthesized BDD models for test generation
J Raik, R Ubar
Proc. of the IEEE European Test Workshop, 145-146, 1998
351998
Combining dynamic slicing and mutation operators for ESL correction
U Repinski, H Hantson, M Jenihhin, J Raik, R Ubar, G Di Guglielmo, ...
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
34*2012
Defect-oriented fault simulation and test generation in digital circuits
W Kuzmicz, W Pleskacz, J Raik, R Ubar
Proceedings of the IEEE 2001. 2nd International Symposium on Quality …, 2001
332001
Sequential circuit test generation using decision diagram models
J Raik, R Ubar
Proceedings of the conference on Design, automation and test in Europe, 145-es, 1999
331999
A systematic literature review on hardware reliability assessment methods for deep neural networks
MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin
ACM Computing Surveys 56 (6), 1-39, 2024
322024
Turbo Tester–diagnostic package for research and training
M Aarna, E Ivask, A Jutman, E Orasson, J Raik, R Ubar, V Vislogubov, ...
Радиоэлектроника и информатика, 69-73, 2003
322003
Ransomware attack as hardware trojan: A feasibility and demonstration study
F Almeida, M Imran, J Raik, S Pagliarini
IEEE Access 10, 44827-44839, 2022
282022
Structurally synthesized binary decision diagrams
A Jutman, A Peder, J Raik, M Tombak, R Ubar
6th International Workshop on Boolean Problems, 271-278, 2004
282004
Structurally synthesized binary decision diagrams
A Jutman, A Peder, J Raik, M Tombak, R Ubar
6th International Workshop on Boolean Problems, 271-278, 2004
282004
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement
M Blyzniuk, I Kazymyra, W Kuzmicz, WA Pleskacz, J Raik, R Ubar
Microelectronics Reliability 41 (12), 2023-2040, 2001
28*2001
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