| The impact of electromigration in copper interconnects on power grid integrity V Mishra, SS Sapatnekar Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 59 | 2013 |
| Predicting electromigration mortality under temperature and product lifetime specifications V Mishra, SS Sapatnekar Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 37 | 2016 |
| A systematic approach for analyzing and optimizing cell-internal signal electromigration G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 486-491, 2014 | 24 | 2014 |
| Cell-internal electromigration: Analysis and pin placement based optimization G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 20 | 2015 |
| Analyzing the electromigration effects on different metal layers and different wire lengths G Posser, V Mishra, R Reis, SS Sapatnekar 2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014 | 20 | 2014 |
| Circuit reliability: from physics to architectures J Fang, S Gupta, SV Kumar, SK Marella, V Mishra, P Zhou, ... Proceedings of the International Conference on Computer-Aided Design, 243-246, 2012 | 20 | 2012 |
| Probabilistic wire resistance degradation due to electromigration in power grids V Mishra, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 16 | 2016 |
| Cell-level signal electromigration SS Sapatnekar, V Mishra, P Jain, G Posser, R Reis US Patent 9,665,680, 2017 | 14 | 2017 |
| Circuit delay variability due to wire resistance evolution under AC electromigration V Mishra, SS Sapatnekar 2015 IEEE International Reliability Physics Symposium, 3D. 3.1-3D. 3.7, 2015 | 13 | 2015 |
| Incorporating the role of stress on electromigration in power grids with via arrays V Mishra, P Jain, SK Marella, SS Sapatnekar Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 12 | 2017 |
| Fast stochastic analysis of electromigration in power distribution networks P Jain, V Mishra, SS Sapatnekar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017 | 7 | 2017 |
| Reducing the signal electromigration effects on different logic gates by cell layout optimization G Posser, L De Paris, V Mishra, P Jain, R Reis, SS Sapatnekar 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2015 | 7 | 2015 |
| Optimizing device reliability effects at the intersection of physics, circuits, and architecture D Sengupta, V Mishra, SS Sapatnekar Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 5 | 2016 |
| Placement optimization of power supply pads based on locality P Zhou, V Mishra, SS Sapatnekar 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 4 | 2013 |
| Electromigration-Induced Interconnect Aging and its Repercussions on the Performance of Nanometer-Scale VLSI Circuits V Mishra University of Minnesota, 2016 | 2 | 2016 |
| Impact on performance, power, area and wirelength using electromigration-aware cells G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar 2015 IEEE International Conference on Electronics, Circuits, and Systems …, 2015 | 2 | 2015 |
| ISVLSI 2017 Additional Reviewers A Srivastava, A Singh, A Ilic, A Barteau, A Dantas, B Ege, ... | | |
Palkesh JainQualcommПодтвержден адрес электронной почты в домене qti.qualcomm.com
