| A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning M Wang, S Lu, D Zhu, J Lin, Z Wang 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 223-226, 2018 | 207 | 2018 |
| Efficient hardware architectures for deep convolutional neural network J Wang, J Lin, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1941-1953, 2017 | 154 | 2017 |
| Hardware accelerator for multi-head attention and position-wise feed-forward in the transformer S Lu, M Wang, S Liang, J Lin, Z Wang 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 84-89, 2020 | 124 | 2020 |
| An Efficient List Decoder Architecture for Polar Codes J Lin, Z Yan Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2015 | 106 | 2015 |
| Accelerating Recurrent Neural Networks: A Memory-Efficient Approach Z Wang, J Lin, Z Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 99 | 2017 |
| Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning D Zhu, S Lu, M Wang, J Lin, Z Wang IEEE Transactions on Circuits and Systems II: Express Briefs 67 (12), 3382-3386, 2020 | 94 | 2020 |
| Efficient decoder design for nonbinary quasicyclic LDPC codes J Lin, J Sha, Z Wang, L Li IEEE Transactions on Circuits and Systems I: Regular Papers 57 (5), 1071-1082, 2010 | 88 | 2010 |
| TIE: energy-efficient tensor train-based inference engine for deep neural network C Deng, F Sun, X Qian, J Lin, Z Wang, B Yuan Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 83 | 2019 |
| An energy-efficient architecture for binary weight convolutional neural networks Y Wang, J Lin, Z Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (2), 280-293, 2017 | 82 | 2017 |
| Evaluations on deep neural networks training using posit number system J Lu, C Fang, M Xu, J Lin, Z Wang IEEE Transactions on Computers 70 (2), 174-187, 2020 | 78 | 2020 |
| Symbol-decision successive cancellation list decoder for polar codes C Xiong, J Lin, Z Yan IEEE Transactions on Signal Processing 64 (3), 675-687, 2015 | 73 | 2015 |
| Flexible LDPC decoder design for multigigabit-per-second applications C Zhang, Z Wang, J Sha, L Li, J Lin IEEE Transactions on Circuits and Systems I: Regular Papers 57 (1), 116-124, 2009 | 73 | 2009 |
| A High Throughput List Decoder Architecture for Polar Codes J Lin, C Xiong, Z Yan IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24 (6), 2378-2391, 2016 | 70 | 2016 |
| E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory M Wang, Z Wang, J Lu, J Lin, Z Wang IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …, 2019 | 65 | 2019 |
| A reduced latency list decoding algorithm for polar codes J Lin, C Xiong, Z Yan Signal Processing Systems (SiPS), 2014 IEEE Workshop on, 0 | 59* | |
| An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks X Xie, J Lin, Z Wang, J Wei IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2936-2949, 2021 | 55 | 2021 |
| DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks M Wang, J Mo, J Lin, Z Wang, L Du 2019 IEEE International Workshop on Signal Processing Systems (SiPS), 178-183, 2019 | 55 | 2019 |
| An efficient VLSI architecture for nonbinary LDPC decoders J Lin, J Sha, Z Wang, L Li IEEE Transactions on Circuits and Systems II: Express Briefs 57 (1), 51-55, 2010 | 51 | 2010 |
| Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes H Cui, F Ghaffari, K Le, D Declercq, J Lin, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 879-891, 2020 | 49 | 2020 |
| Low complexity message passing detection algorithm for large-scale MIMO systems J Zeng, J Lin, Z Wang IEEE Wireless Communications Letters 7 (5), 708-711, 2018 | 47 | 2018 |