| Circuit-level techniques for reliable physically uncloneable functions V Vivekraja, L Nazhandali 2009 IEEE International Workshop on Hardware-Oriented Security and Trust, 30-35, 2009 | 70 | 2009 |
| From statistics to circuits: Foundations for future physical unclonable functions I Kim, A Maiti, L Nazhandali, P Schaumont, V Vivekraja, H Zhang Towards Hardware-Intrinsic Security: Foundations and Practice, 55-78, 2010 | 42 | 2010 |
| Feedback based supply voltage control for temperature variation tolerant PUFs V Vivekraja, L Nazhandali 2011 24th Internatioal Conference on VLSI Design, 214-219, 2011 | 25 | 2011 |
| A highly stable leakage-based silicon physical unclonable functions D Ganta, V Vivekraja, K Priya, L Nazhandali 2011 24th Internatioal Conference on VLSI Design, 135-140, 2011 | 22 | 2011 |
| Fine-grained sparsity computations in systolic array PG Meyer, TK Hah, RR Huang, R Diamant, V Vivekraja US Patent 11,803,736, 2023 | 6 | 2023 |
| Emulating fine-grained sparsity in a systolic array PG Meyer, TK Hah, RR Huang, R Diamant, V Vivekraja US Patent 11,500,962, 2022 | 4 | 2022 |
| Low-power, stable and secure on-chip identifiers design V Vivekraja Virginia Tech, 2010 | 4 | 2010 |
| Acceleration of neural networks with stacks of convolutional layers TK Hah, RR Huang, RJ Heaton, R Diamant, V Vivekraja US Patent 12,008,469, 2024 | 2 | 2024 |
| Data compression using instruction set architecture T Tohara, V Vivekraja, A Valliappan, A Bushev, J Jaffari US Patent App. 18/525,083, 2024 | 1 | 2024 |
| Low latency neural network model loading D Borkovic, I Minkin, V Vivekraja, RJ Heaton, RR Huang US Patent 11,182,314, 2021 | 1 | 2021 |
| Multinomial distribution on an integrated circuit Y Zhou, V Vivekraja, R Diamant US Patent 10,997,277, 2021 | 1 | 2021 |
| Accelerated convolution of neural networks TK Hah, RR Huang, RJ Heaton, R Diamant, V Vivekraja US Patent 12,205,013, 2025 | | 2025 |
| Fine-grained sparsity computations in systolic array PG Meyer, TK Hah, RR Huang, R Diamant, V Vivekraja US Patent 12,182,695, 2024 | | 2024 |
| NEURAL NETWORK TRAINING UNDER MEMORY RESTRAINT S Sengupta, RR Renfu, R Diamant, V Vivekraja US Patent App. 18/798,323, 2024 | | 2024 |
| Dropout layer in a neural network processor J Gai, H Zheng, A Jain, RR Huang, V Vivekraja US Patent 12,159,218, 2024 | | 2024 |
| Emulating fine-grained sparsity in a systolic array PG Meyer, TK Hah, RR Huang, R Diamant, V Vivekraja US Patent 12,130,885, 2024 | | 2024 |
| Neural network training under memory restraint S Sengupta, RR Huang, R Diamant, V Vivekraja US Patent 12,106,222, 2024 | | 2024 |
| Reducing computation in neural networks using self-modifying code V Vivekraja, RR Huang, Y Zhou, R Diamant, RJ Heaton US Patent 12,073,199, 2024 | | 2024 |
| Neural network training in a distributed system V Vivekraja, TK Hah, RR Huang, R Diamant, RJ Heaton US Patent App. 18/221,454, 2024 | | 2024 |
| Sequence of operations in an simd vliw processor for machine-learning computations V Vivekraja, T Tohara, R Tusi, A Tuoheti, J Jaffari, V Fruchter, D Vakrat, ... US Patent App. 18/527,063, 2024 | | 2024 |
