| Automatic abstraction for verification of cyber-physical systems RA Thacker, KR Jones, CJ Myers, H Zheng Proceedings of the 1st ACM/IEEE International Conference on Cyber-Physical …, 2010 | 101 | 2010 |
| Timed circuits: A new paradigm for high-speed design CJ Myers, W Belluomini, K Kallpack, E Peskin, H Zheng Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 46 | 2001 |
| Self-refereed on-chip jitter measurement circuit using Vernier oscillators T Xia, H Zheng, J Li, A Ginawi IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design …, 2005 | 42 | 2005 |
| Architectural synthesis of timed asynchronous systems BM Bachman, H Zheng, CJ Myers Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999 | 37 | 1999 |
| Modular verification of timed circuits using automatic abstraction H Zheng, E Mercer, C Myers IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 36 | 2003 |
| Specification and compilation of timed systems H Zheng Dept. of Electrical Engineering, University of Utah, 1998 | 29 | 1998 |
| An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis Z Zhang, W Serwe, J Wu, T Yoneda, H Zheng, C Myers Science of Computer Programming 118, 24-39, 2016 | 21 | 2016 |
| Verification of timed circuits with failure-directed abstractions H Zheng, CJ Myers, D Walter, S Little, T Yoneda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 21 | 2006 |
| Soft error analysis and optimizations of C-elements in asynchronous circuits B Vaidyanathan, Y Xie, N Vijaykrishnan, H Zheng Proc. 2nd Workshop Syst. Effects Logic Soft Errors, 1-4, 2006 | 17 | 2006 |
| Stamina: Stochastic approximate model-checker for infinite-state analysis T Neupane, CJ Myers, C Madsen, H Zheng, Z Zhang Computer Aided Verification: 31st International Conference, CAV 2019, New …, 2019 | 16 | 2019 |
| Compositional reachability analysis for efficient modular verification of asynchronous designs H Zheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 16 | 2010 |
| Mining message flows from system-on-chip execution traces MR Ahmed, H Zheng, P Mukherjee, MC Ketkar, J Yang 2021 22nd international symposium on quality electronic design (ISQED), 374-380, 2021 | 15 | 2021 |
| Modular model checking of large asynchronous designs with efficient abstraction refinement H Zheng, H Yao, T Yoneda IEEE Transactions on Computers 59 (4), 561-573, 2010 | 15 | 2010 |
| Automated interface refinement for compositional verification H Yao, H Zheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 15 | 2009 |
| Formal analysis of a fault-tolerant routing algorithm for a network-on-chip Z Zhang, W Serwe, J Wu, T Yoneda, H Zheng, C Myers Formal Methods for Industrial Critical Systems: 19th International …, 2014 | 12 | 2014 |
| Modular synthesis of timed circuits using partial orders on LPNs EG Mercer, CJ Myers, T Yoneda, H Zheng Electronic Notes in Theoretical Computer Science 65 (6), 180-201, 2002 | 12 | 2002 |
| Mining message flows using recurrent neural networks for system-on-chip designs Y Cao, P Mukherjee, M Ketkar, J Yang, H Zheng 2020 21st International Symposium on Quality Electronic Design (ISQED), 389-394, 2020 | 11 | 2020 |
| Approximation techniques for stochastic analysis of biological systems T Neupane, Z Zhang, C Madsen, H Zheng, CJ Myers Automated Reasoning for Systems Biology and Medicine, 327-348, 2019 | 11 | 2019 |
| A post-silicon trace analysis approach for system-on-chip protocol debug Y Cao, H Zheng, H Palombo, S Ray, J Yang 2017 IEEE International Conference on Computer Design (ICCD), 177-184, 2017 | 11 | 2017 |
| Timing jitter characterization for mixed-signal production test using the interpolation algorithm T Xia, H Zheng IEEE Transactions on Industrial Electronics 54 (2), 1014-1023, 2007 | 9 | 2007 |
Chris MyersUniversity of UtahOverená e-mailová adresa na: ece.utah.edu
