RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to H Pettenghi, R Chaves, L Sousa
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (6), 1487-1500, 2012
67 2012 Multi-threshold threshold logic circuit design using resonant tunnelling devices MJ Avedillo, JM Quintana, H Pettenghi, PM Kelly, CJ Thompson
Electronics Letters 39 (21), 1502-1504, 2003
60 2003 Using multi-threshold threshold gates in RTD-based logic design: A case study H Pettenghi, MJ Avedillo, JM Quintana
Microelectronics Journal 39 (2), 241-247, 2008
39 2008 Increased logic functionality of clocked series-connected RTDs MJ Avedillo, JM Quintana, HP Roldán
Nanotechnology, IEEE Transactions on 5 (5), 606-611, 2006
36 2006 Method to design general RNS reverse converters for extended moduli sets H Pettenghi, R Chaves, L Sousa
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (12), 877-881, 2013
32 2013 Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors MJ Avedillo, JM Quintana, H Pettenghi
IEEE Transactions on Circuits and Systems II: Express Briefs 53 (5), 334-338, 2006
30 2006 RNS Arithmetic Units for Modulo {2^ n+-k} PM Matutino, H Pettenghi, R Chaves, L Sousa
2012 15th Euromicro Conference on Digital System Design, 795-802, 2012
20 2012 Improved nanopipelined RTD adder using generalized threshold gates H Pettenghi, MJ Avedillo, JM Quintana
IEEE Transactions on Nanotechnology 10 (1), 155-162, 2009
20 2009 Efficient implementation of modular multiplication by constants applied to RNS reverse converters R de Matos, R Paludo, N Chervyakov, PA Lyakhov, H Pettenghi
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
19 2017 Operation limits for RTD-based MOBILE circuits JM Quintana, MJ Avedillo, J Nunez, HP Roldán
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (2), 350-363, 2008
18 2008 Logic models supporting the design of MOBILE-based RTD circuits MJ Avedillo, JM Quintana, H Pettenghi
2005 IEEE International Conference on Application-Specific Systems …, 2005
17 2005 Single phase clock scheme for MOBILE logic gates H Pettenghi, MJ Avedillo, JM Quintana
Electronics Letters 42 (24), 1382-1383, 2006
15 2006 A novel contribution to the RTD-based threshold logic family H Pettenghi, MJ Avedillo, JM Quintana
2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2350-2353, 2008
13 2008 Useful logic blocks based on clocked series-connected RTDs H Pettenghi, MJ Avedillo, JM Quintana
4th IEEE Conference on Nanotechnology, 2004., 593-595, 2004
10 2004 Efficient implementation of multi-moduli architectures for binary-to-rns conversion H Pettenghi, L Sousa, JA Ambrose
17th Asia and South Pacific Design Automation Conference, 819-824, 2012
9 2012 DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks JA Ambrose, H Pettenghi, L Sousa
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 620-625, 2013
8 2013 Multiplierbased binary-to-RNS converter modulo {2n±k} PM Matutino, H Pettenghi, R Chaves, L Sousa
Proc. 26th Conf. DCIS, 125-130, 2011
8 2011 Towards the integration of reverse converters into the RNS channels L Sousa, R Paludo, P Martins, H Pettenghi
IEEE Transactions on Computers 69 (3), 342-348, 2019
7 2019 RNS reverse converters for moduli sets with dynamic ranges of 9n-bit H Pettenghi, R de Matos, A Molahosseini
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 143-146, 2016
7 2016 Method for designing efficient mixed radix multipliers H Pettenghi, F Pratas, L Sousa
Circuits, Systems, and Signal Processing 33, 3165-3193, 2014
7 2014 
Leonel SousaINESC-ID, Instituto Superior TécnicoOverená e-mailová adresa na: inesc-id.pt
