| Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping S Ahish, D Sharma, YBN Kumar, MH Vasantha IEEE Transactions on Electron Devices 63 (1), 288-295, 2015 | 159 | 2015 |
| Design and analysis of multiplier using approximate 4-2 compressor KM Reddy, MH Vasantha, YBN Kumar, D Dwivedi AEU-International Journal of Electronics and Communications 107, 89-97, 2019 | 89 | 2019 |
| Slew-rate and gain enhancement in two stage operational amplifiers AP Perez, YBN Kumar, E Bonizzoni, F Maloberti 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2485-2488, 2009 | 71 | 2009 |
| A gracefully degrading and energy-efficient fault tolerant NoC using spare core BNK Reddy, MH Vasantha, YBN Kumar 2016 IEEE computer society annual symposium on VLSI (ISVLSI), 146-151, 2016 | 70 | 2016 |
| System level fault-tolerance core mapping and FPGA-based verification of NoC NKR Becchu, VM Harishchandra, NKY Balachandra Microelectronics Journal 70, 16-26, 2017 | 61 | 2017 |
| High-performance and energy-efficient fault-tolerance core mapping in NoC NKR Beechu, VM Harishchandra, NKY Balachandra Sustainable Computing: Informatics and Systems 16, 1-10, 2017 | 57 | 2017 |
| A 1-V, 3-GHz strong-arm latch voltage comparator for high speed applications RK Siddharth, YJ Satyanarayana, YBN Kumar, MH Vasantha, E Bonizzoni IEEE Transactions on Circuits and Systems II: Express Briefs 67 (12), 2918-2922, 2020 | 51 | 2020 |
| Hardware implementation of fault tolerance NoC core mapping NKR Beechu, V Moodabettu Harishchandra, NK Yernad Balachandra Telecommunication Systems 68, 621-630, 2018 | 46 | 2018 |
| Communication energy constrained spare core on NoC BNK Reddy, MH Vasantha, YBN Kumar, D Sharma 2015 6th international conference on computing, communication and networking …, 2015 | 44 | 2015 |
| An energy-efficient fault-aware core mapping in mesh-based network on chip systems NKR Beechu, VM Harishchandra, NKY Balachandra Journal of Network and Computer Applications 105, 79-87, 2018 | 43 | 2018 |
| Approximate radix-8 booth multiplier for low power and high speed applications B Boro, KM Reddy, YBN Kumar, MH Vasantha Microelectronics Journal 101, 104816, 2020 | 32 | 2020 |
| Energy-aware and reliability-aware mapping for NoC-based architectures NKR Beechu, V Moodabettu Harishchandra, NK Yernad Balachandra Wireless Personal Communications 100 (2), 213-225, 2018 | 31 | 2018 |
| Design of approximate booth squarer for error-tolerant computing KM Reddy, MH Vasantha, YBN Kumar, D Dwivedi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (5 …, 2020 | 30 | 2020 |
| Reversible full/half adder with optimum power dissipation M Aditya, YBN Kumar, MH Vasantha 2016 10th International Conference on Intelligent Systems and Control (ISCO …, 2016 | 30 | 2016 |
| A fine grained position for modular core on NoC BNK Reddy, MH Vasantha, YBN Kumar, D Sharma 2015 International Conference on Computer, Communication and Control (IC4), 1-4, 2015 | 28 | 2015 |
| A 0.5 V low power OTA-C low pass filter for ECG detection R Rakhi, AD Taralkar, MH Vasantha, NK YB 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 589-593, 2017 | 25 | 2017 |
| A 1.2 V, highly reliable RHBD 10T SRAM cell for aerospace application SS Dohar, RK Siddharth, MH Vasantha, NK YB IEEE Transactions on Electron Devices 68 (5), 2265-2270, 2021 | 24 | 2021 |
| Design of approximate dividers for error tolerant applications KM Reddy, MH Vasantha, YBN Kumar, D Dwivedi 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 22 | 2018 |
| Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor S Ahish, D Sharma, MH Vasantha, YBN Kumar Superlattices and Microstructures 94, 119-130, 2016 | 20 | 2016 |
| Design of low power 5-bit hybrid flash ADC SM Mayur, RK Siddharth, YBN Kumar, MH Vasantha 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 343-348, 2016 | 18 | 2016 |
