| 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications R Carter, J Mazurier, L Pirro, JU Sachse, P Baars, J Faul, C Grass, ... 2016 IEEE International Electron Devices Meeting (IEDM), 2.2. 1-2.2. 4, 2016 | 322 | 2016 |
| Formation of silicided surfaces for silicon/carbon source/drain regions T Kammler, P Press, R Stephan, S Beyer US Patent App. 11/550,631, 2007 | 107 | 2007 |
| Embedded strain layer in thin SOI transistors and a method of forming the same J Hoentschel, A Wei, M Horstmann, T Kammler US Patent 7,399,663, 2008 | 106 | 2008 |
| Double gate and tri-gate transistor formed on a bulk substrate and method for forming the transistor A Wei, R Mulfinger, T Scheiper, T Kammler US Patent App. 12/473,610, 2009 | 96 | 2009 |
| Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies LT Su, J Pellerin, SF Huang, M Khare, D Schepis, K Rim, S Liming, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 96 | 2005 |
| High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005 | 69 | 2005 |
| Performance and low-frequency noise of 22-nm FDSOI down to 4.2 K for cryogenic applications BC Paz, M Cassé, C Theodorou, G Ghibaudo, T Kammler, L Pirro, M Vinet, ... IEEE Transactions on Electron Devices 67 (11), 4563-4567, 2020 | 56 | 2020 |
| Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors J Hoentschel, A Wei, T Kammler, M Raab US Patent 7,586,153, 2009 | 52 | 2009 |
| Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same A Wei, T Kammler, J Hoentschel, M Horstmann US Patent 7,659,213, 2010 | 50 | 2010 |
| Technique for transferring strain into a semiconductor region T Kammler, M Gerhardt, F Wirbeleit US Patent 7,494,906, 2009 | 49 | 2009 |
| Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material K Wieczorek, T Kammler, M Horstmann US Patent 6,838,363, 2005 | 48 | 2005 |
| Technique for providing multiple stress sources in NMOS and PMOS transistors J Hoentschel, A Wei, M Horstmann, T Kammler US Patent 7,329,571, 2008 | 44 | 2008 |
| Technique for forming a contact insulation layer with enhanced stress transfer efficiency T Kammler, A Wei, M Lenski US Patent 7,354,838, 2008 | 40 | 2008 |
| SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same A Wei, T Kammler, J Hoentschel, M Horstmann US Patent 7,829,421, 2010 | 37 | 2010 |
| Method for forming double gate and tri-gate transistors on a bulk substrate A Wei, R Mulfinger, T Scheiper, T Kammler US Patent 8,114,746, 2012 | 36 | 2012 |
| Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process T Kammler, A Wei, I Ostermay US Patent 8,053,273, 2011 | 36 | 2011 |
| Tuning nickel silicide properties using a lamp based RTA, a heat conduction based RTA or a furnace anneal S Waidmann, V Kahlert, C Streck, P Press, T Kammler, K Dittmar, I Zienert, ... Microelectronic Engineering 83 (11-12), 2282-2286, 2006 | 35 | 2006 |
| Pseudoepitaxial transrotational structures in 14 nm-thick NiSi layers on [001] silicon A Alberti, C Bongiorno, B Cafra, G Mannino, E Rimini, T Metzger, ... Structural Science 61 (5), 486-491, 2005 | 34 | 2005 |
| Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions A Wei, T Kammler, J Hoentschel, M Horstmann, P Javorka, J Bloomquist US Patent 7,696,052, 2010 | 32 | 2010 |
| In situ formed halo region in a transistor device T Kammler, A Wei, H Bierstedt US Patent App. 11/203,848, 2006 | 32 | 2006 |