Haridimos T. Vergos

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	Všetky	Od 2020
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Spoluautori

Dimitris NikolosProfessor, Computer Engineering & Informatics Dept, University of PatrasOverená e-mailová adresa na: ceid.upatras.gr
Constantinos EfstathiouProfessor, Dept. of Informatics and Computer Engineering, University of West AtticaOverená e-mailová adresa na: uniwa.gr
Dimitris BakalisAssistant Professor, University of PatrasOverená e-mailová adresa na: physics.upatras.gr
Giorgos DimitrakopoulosProfessor, ECE, Democritus University of ThraceOverená e-mailová adresa na: ee.duth.gr
John KalamatianosFellow Design Engineer, AMD ResearchOverená e-mailová adresa na: amd.com
Maciej BellosOverená e-mailová adresa na: ceid.upatras.gr
Yiorgos TsiatouhasUniversity of IoanninaOverená e-mailová adresa na: cse.uoi.gr
Xrysovalantis KavousianosUniversity of IoanninaOverená e-mailová adresa na: cs.uoi.gr
George P. AlexiouProfessor of Computer Eng, Universtity of Patras, GreeceOverená e-mailová adresa na: upatras.gr
Spyros VoulgarisAthens University of Economics and BusinessOverená e-mailová adresa na: aueb.gr
m nicolaidisTIMA LaboratoryOverená e-mailová adresa na: imag.fr
Olympia GiannouR&D Computer and Informatics EngineerOverená e-mailová adresa na: upatras.gr
Georgios KeramidasAssistant Professor, Aristotle University of Thessaloniki / Think Silicon S.A. / Applied MaterialsOverená e-mailová adresa na: csd.auth.gr

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Haridimos T. Vergos

Professor, Computer Engineering & Informatics Dept, University of Patras

Overená e-mailová adresa na: ceid.upatras.gr - Domovská stránka

Computer Arithmetic VLSI Design VLSI Testing Computer Architecture


Názov Zoradiť podľa citácií Zoradiť podľa roka Zoradiť podľa názvu	Citované v Citované v	Rok
High-speed parallel-prefix modulo adders L Kalampoukas, D Nikolos, C Efstathiou, HT Vergos, J Kalamatianos IEEE Transactions on Computers 49 (7), 673-680, 2000	207	2000
Diminished-one modulo adder design HT Vergos, C Efstathiou, D Nikolos IEEE Transactions on Computers 51 (12), 1389-1399, 2002	203	2002
Fast parallel-prefix modulo adders C Efstathiou, HT Vergos, D Nikolos IEEE Transactions on Computers 53 (9), 1211-1216, 2004	131	2004
Efficient diminished-1 modulo multipliers C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos IEEE Transactions on Computers 54 (4), 491-496, 2005	97	2005
Modified Booth modulo multipliers C Efstathiou, HT Vergos, D Nikolos IEEE Transactions on Computers 53 (3), 370-374, 2004	93	2004
On Modulo Adder Design HT Vergos, G Dimitrakopoulos IEEE Transactions on Computers 61 (2), 173-186, 2010	87	2010
Design of efficient modulo multipliers HT Vergos, C Efstathiou IET Computers & Digital Techniques 1 (1), 49-57, 2007	85	2007
Modulo adder design using select-prefix blocks C Efstathiou, HT Vergos, D Nikolos IEEE Transactions on Computers 52 (11), 1399-1406, 2003	83	2003
A Unifying Approach for Weighted and Diminished-1 Modulo Addition HT Vergos, C Efstathiou IEEE Transactions on Circuits and Systems II: Express Briefs 55 (10), 1041-1045, 2008	68	2008
New architectures for modulo adders G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou 2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005	46	2005
Efficient modulo adder architectures HT Vergos, C Efstathiou Integration, the VLSI Journal 42 (2), 149-157, 2009	39	2009
Handling zero in diminished-one modulo adders C Efstathiou, HT Vergos, D Nikolos International journal of electronics 90 (2), 133-144, 2003	35	2003
Performance recovery in direct-mapped faulty caches via the use of a very small fully associative spare cache HT Vergos, D Nikolos Proceedings of 1995 IEEE International Computer Performance and …, 1995	28	1995
On the design of modulo subtractors and adders/subtractors E Vassalos, D Bakalis, HT Vergos Circuits, Systems, and Signal Processing 30 (6), 1445-1461, 2011	21	2011
Diminished-1 modulo squarer design HT Vergos, C Efstathiou IEE Proceedings-Computers and Digital Techniques 152 (5), 561-566, 2005	21	2005
Efficient fault tolerant cache memory design HT Vergos, D Nikolos Microprocessing and microprogramming 41 (2), 153-169, 1995	21	1995
RNS assisted image filtering and edge detection E Vassalos, D Bakalis, HT Vergos 2013 18th International Conference on Digital Signal Processing (DSP), 1-6, 2013	20	2013
A family of parallel-prefix modulo adders G Dimitrakopoulos, HT Vergos, D Nikolos, C Efstathiou Proceedings IEEE International Conference on Application-Specific Systems …, 2003	20	2003
On the design of efficient modular adders HT Vergos, C Efstathiou Journal of Circuits, Systems, and Computers 14 (05), 965-972, 2005	19	2005
Modified Booth 1's complement and modulo multipliers C Efstathiou, HT Vergos ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000	19	2000

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