| Gate-all-around nanowire junctionless transistor-based hydrogen gas sensor S Mokkapati, N Jaiswal, M Gupta, A Kranti IEEE Sensors Journal 19 (13), 4758-4764, 2019 | 45 | 2019 |
| Modeling Short-Channel Effects in Core–Shell Junctionless MOSFET N Jaiswal, A Kranti IEEE Transactions on Electron Devices 66 (1), 292-299, 2018 | 31 | 2018 |
| A model for gate-underlap-dependent short-channel effects in junctionless MOSFET N Jaiswal, A Kranti IEEE Transactions on Electron Devices 65 (3), 881-887, 2018 | 29 | 2018 |
| Modeling short-channel effects in asymmetric junctionless MOSFETs with underlap N Jaiswal, A Kranti IEEE Transactions on Electron Devices 65 (9), 3669-3675, 2018 | 27 | 2018 |
| Limits on Hysteresis-Free Sub-60 mV/Decade Operation of MFIS Nanowire Transistor S Semwal, VP Reddy, N Jaiswal, A Kranti IEEE Transactions on Electron Devices 67 (9), 3868-3875, 2020 | 17 | 2020 |
| Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications RK Nirala, AS Roy, S Semwal, N Rai, A Kranti Japanese Journal of Applied Physics 62 (SC), SC1040, 2023 | 4 | 2023 |
| Incorporating Quantum Effects in Ultralow Power (ULP) Subthreshold Logic Design With Junctionless Nanowire Transistor N Rai, K Ahuja, S Semwal, A Kranti IEEE Transactions on Electron Devices 69 (7), 3983-3989, 2022 | 4 | 2022 |
| Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor N Rai, S Semwal, RK Nirala, A Kranti IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 3 | 2023 |
| Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers N Jaiswal, R Gamad Circuits and Systems 6 (03), 81-92, 2015 | 3 | 2015 |
| Ultra-low-power subthreshold logic with germanium junctionless transistors P Shrivas, N Jaiswal, S Semwal, A Kranti Semiconductor Science and Technology 36 (7), 075011, 2021 | 2 | 2021 |
| Sensitivity implications for programmable transistor based 1T-DRAM RK Nirala, S Semwal, YV Bhuvaneshwari, N Rai, A Kranti Solid-State Electronics 194, 108353, 2022 | 1 | 2022 |
| Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET S Semwal, N Rai, RK Nirala, M Gupta, A Kranti 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2024 | | 2024 |
| Architecture Dependent Constraint-Aware RFET Based 1T-DRAM S Semwal, RK Nirala, N Rai, A Kranti 2023 International VLSI Symposium on Technology, Systems and Applications …, 2023 | | 2023 |
| Design optimization of double gate junctionless MOSFET for enhanced short channel immunity N Jaiswal, A Kranti Discipline of Electrical Engineering, IIT Indore, 2020 | | 2020 |
| Scalability and Vth sensitivity assessment of core-shell junctionless MOSFET N Jaiswal, A Kranti International Conference on Solid State Devices and Materials (SSDM 2019 …, 2019 | | 2019 |
| Influence of gate-source/drain underlap on performance of junctionless transistor N Jaiswal, A Kranti 6th International Symposium on Integrated Functionalities (ISIF 2017), 126, 2017 | | 2017 |
| Three Levels Interconnect Signaling in On-Chip High Speed SerDes Transceiver for Multi-Module SoC Communication N Jaiswal, R Gamad Proceedings of the Sixth International Conference on Computer and …, 2015 | | 2015 |
Y. V. BhuvaneshwariPostdoctoral Researcher at IMEC BelgiumOverená e-mailová adresa na: imec.be
