| Robust sliding-mode control for maximum power point tracking of photovoltaic power systems with quantized input signal H Aminnejhad, S Kazeminia, M Aliasghary Optik 247, 167983, 2021 | 22 | 2021 |
| A 80-MHz-to-410-MHz 16-phases DLL based on improved dead-zone open-loop phase detector and reduced-gain charge pump S Kazeminia, SS Mowloodi, K Hadidi Journal of Circuits, Systems and Computers 24 (01), 1550001, 2015 | 17 | 2015 |
| A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector S Kazeminia, K Hadidi, A Khoei 2013 21st Iranian Conference on Electrical Engineering (ICEE), 1-5, 2013 | 17 | 2013 |
| On matching properties of R-2R ladders in high performance digital-to-analog converters S Kazeminia, Y Hesamiafshar, K Hadidi, A Khoei 2010 18th Iranian Conference on Electrical Engineering, 432-436, 2010 | 17 | 2010 |
| High speed high precision voltage-mode MAX and MIN circuits SK Nia, A Khoei, K Hadidi 13th IEEE International Conference on Electronics, Circuits and Systems, 2007 | 16 | 2007 |
| High speed high precision voltage-mode MAX and MIN circuits SK Nia, A Khoei, K Hadidi Journal of Circuits, Systems, and Computers 16 (02), 233-244, 2007 | 16 | 2007 |
| A 800MS/s, 150µV input-referred offset single-stage latched comparator S Kazeminia, S Mahdavi 2016 MIXDES-23rd international conference mixed design of integrated …, 2016 | 15 | 2016 |
| A wide-range low-jitter PLL based on fast-response VCO and simplified straightforward methodology of loop stabilization in integer-N PLLs S Kazeminia, K Hadidi, A Khoei Journal of Circuits, Systems and Computers 24 (07), 1550104, 2015 | 15 | 2015 |
| A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process S Kazeminia, M Mousazadeh, K Hadidi, A Khoei IEICE transactions on electronics 94 (4), 635-640, 2011 | 14 | 2011 |
| Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption M Soleimani, A Khoei, K Hadidi, SK Nia 2009 European Conference on Circuit Theory and Design, 351-354, 2009 | 14 | 2009 |
| High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection S Kazeminia, M Mousazadeh, K Hadidi, A Khoei 2010 IEEE Asia Pacific Conference on Circuits and Systems, 216-219, 2010 | 13 | 2010 |
| Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs S Kazeminia, O Shino, E Haghighi, K Hadidi 2013 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2013 | 12 | 2013 |
| A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability S Kazeminia, R Abdollahi, A Hejazi Analog Integrated Circuits and Signal Processing 94, 507-517, 2018 | 11 | 2018 |
| Frequency-range enhanced delay locked loop based on varactor-loaded and current-controlled delay elements S Kazeminia AEU-International Journal of Electronics and Communications 127, 153477, 2020 | 9 | 2020 |
| Bulk controlled offset cancellation mechanism for single-stage latched comparator S Kazeminia, S Mahdavi, R Gholamnejad 2016 MIXDES-23rd International Conference Mixed Design of Integrated …, 2016 | 8 | 2016 |
| Wide-range 16-phases DLL based on improved dead-zone phase detector and reduced gain charge pump S Kazeminia, SS Mowloodi, K Hadidi 2014 22nd Iranian Conference on Electrical Engineering (ICEE), 133-138, 2014 | 7 | 2014 |
| A 17 MS/s SAR ADC with energy-efficient switching strategy S Mahdavi, S Kazeminia, K Hadidi Analog Integrated Circuits and Signal Processing 103, 223-236, 2020 | 6 | 2020 |
| Highly-matched sub-ADC cells for pipeline analogue-to-digital converters S Kazeminia, S Mahdavi International Journal of Electronics 106 (12), 1785-1813, 2019 | 6 | 2019 |
| Speed enhancement and kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters S Kazeminia, O Shino, E Haghighi, K Hadidi International Journal of Electronics Letters 5 (1), 99-114, 2017 | 6 | 2017 |
| A low-jitter leakage-free digitally calibrated phase locked loop S Kazeminia, A Soltani Computers & Electrical Engineering 88, 106865, 2020 | 5* | 2020 |
Abdollah KhoeiProfessor of Electrical EngineeringOverená e-mailová adresa na: urmia.ac.ir
