| GPU computing gems jade edition W Hwu Elsevier, 2011 | 490* | 2011 |
| Event-driven gate-level simulation with GP-GPUs D Chatterjee, A DeOrio, V Bertacco Proceedings of the 46th Annual Design Automation Conference, 557-562, 2009 | 145 | 2009 |
| GCS: High-performance gate-level simulation with GPGPUs D Chatterjee, A DeOrio, V Bertacco 2009 Design, Automation & Test in Europe Conference & Exhibition, 1332-1337, 2009 | 102 | 2009 |
| Simulation-based signal selection for state restoration in silicon debug D Chatterjee, C McCarter, V Bertacco 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 595-601, 2011 | 93 | 2011 |
| SAGA: SystemC acceleration on GPU architectures S Vinco, D Chatterjee, V Bertacco, F Fummi Proceedings of the 49th Annual Design Automation Conference, 115-120, 2012 | 51 | 2012 |
| Gate-level simulation with GPU computing D Chatterjee, A Deorio, V Bertacco ACM Transactions on Design Automation of Electronic Systems (TODAES) 16 (3 …, 2011 | 36 | 2011 |
| SystemC simulation on GP-GPUs: CUDA vs. OpenCL N Bombieri, S Vinco, V Bertacco, D Chatterjee Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012 | 21 | 2012 |
| Checking architectural outputs instruction-by-instruction on acceleration platforms D Chatterjee, A Koyfman, R Morad, A Ziv, V Bertacco Proceedings of the 49th Annual Design Automation Conference, 955-961, 2012 | 19 | 2012 |
| On the use of GP-GPUs for accelerating compute-intensive EDA applications V Bertacco, D Chatterjee, N Bombieri, F Fummi, S Vinco, AM Kaushik, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 15 | 2013 |
| EQUIPE: Parallel equivalence checking with GP-GPUs D Chatterjee, V Bertacco 2010 IEEE International Conference on Computer Design, 486-493, 2010 | 14 | 2010 |
| Gate-Level Logic Simulator Using Multiple Processor Architectures V Bertacco, D Chatterjee, A Deorio, THEROFTHEUOF MICHIGAN US Patent 8,738,349, 2014 | 11 | 2014 |
| Study of the potential of alternative crops by integration of multisource data using a neuro‐fuzzy technique A Sarkar, A Majumdar, S Chatterjee, D Chatterjee, SS Ray, B Kartikeyan International Journal of Remote Sensing 29 (19), 5479-5493, 2008 | 7 | 2008 |
| Instruction-by-instruction checking on acceleration platforms D Chatterjee, A Koyfman, R Morad, A Ziv US Patent 8,601,418, 2013 | 6 | 2013 |
| Approximating checkers for simulation acceleration B Mammo, D Chatterjee, D Pidan, A Nahir, A Ziv, R Morad, V Bertacco 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 153-158, 2012 | 6 | 2012 |
| High performance gate-level simulation with gp-gpu computing V Bertacco, D Chatterjee Proceedings of 2011 International Symposium on VLSI Design, Automation and …, 2011 | 6 | 2011 |
| Addressing verification challenges of heterogeneous systems based on IBM POWER9 K. D. Schubert, S. S. Abrar, D. Averill, E. Bauman, A. C. Brown, R. Cash, D ... IBM Journal of Research and Development 62 (4), 2018 | 5 | 2018 |
| ArChiVED: Architectural checking via event digests for high performance validation CH Hsu, D Chatterjee, R Morad, R Ga, V Bertacco 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 4 | 2014 |
| Activity-based refinement for abstraction-guided simulation D Chatterjee, V Bertacco 2009 IEEE International High Level Design Validation and Test Workshop, 146-153, 2009 | 4 | 2009 |
| Circuit design verification in a hardware accelerated simulation environment using breakpoints R Batra, D Chatterjee, CR Jones, CM Riedl, JA SCHUMANN, KE YOKUM US Patent 9,939,487, 2018 | 3 | 2018 |
| Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation P Umbarger, D Chatterjee, K Yokum, JA Schumann, B Cockcroft, ... US Patent 11,475,191, 2022 | 2 | 2022 |
Valeria BertaccoMary Lou Dorf Professor, Computer Science and Engineering, University of MichiganOverená e-mailová adresa na: umich.edu