Spremljaj
Shubham Jain
Shubham Jain
Research Staff Member, IBM T.J. Watson Research Center
Preverjeni e-poštni naslov na ibm.com
Naslov
Navedeno
Navedeno
Leto
Computing in Memory with Spin-Transfer Torque Magnetic RAM
S Jain, A Ranjan, K Roy, A Raghunathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 470-483, 2018
4022018
RxNN: A framework for evaluating deep neural networks on resistive crossbars
S Jain, A Sengupta, K Roy, A Raghunathan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
141*2020
Resistive crossbars as approximate hardware building blocks for machine learning: Opportunities and challenges
I Chakraborty, M Ali, A Ankit, S Jain, S Roy, S Sridharan, A Agrawal, ...
Proceedings of the IEEE 108 (12), 2276-2310, 2020
1032020
RaPiD: AI accelerator for ultra-low precision training and inference
S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
962021
Compensated-DNN: Energy efficient low-precision deep neural networks by compensating quantization errors
S Jain, S Venkataramani, V Srinivasan, J Choi, P Chuang, L Chang
Proceedings of the 55th annual design automation conference, 1-6, 2018
802018
Efficient AI system design with cross-layer approximate computing
S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ...
Proceedings of the IEEE 108 (12), 2232-2250, 2020
612020
Cxdnn: Hardware-software compensation methods for deep neural networks on resistive crossbar systems
S Jain, A Raghunathan
ACM Transactions on Embedded Computing Systems (TECS) 18 (6), 1-23, 2019
612019
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks
S Sen, S Jain, S Venkataramani, A Raghunathan
IEEE Transactions on Computers 68 (6), 912-925, 2018
572018
TxSim: Modeling training of deep neural networks on resistive crossbar systems
S Roy, S Sridharan, S Jain, A Raghunathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 730-738, 2021
542021
Biscaled-dnn: Quantizing long-tailed datastructures with two scale factors for deep neural networks
S Jain, S Venkataramani, V Srinivasan, J Choi, K Gopalakrishnan, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
502019
TiM-DNN: Ternary in-memory accelerator for deep neural networks
S Jain, SK Gupta, A Raghunathan
IEEE transactions on very large scale integration (VLSI) systems 28 (7 …, 2020
482020
X-mann: A crossbar based architecture for memory augmented neural networks
A Ranjan, S Jain, JR Stevens, D Das, B Kaul, A Raghunathan
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
482019
A heterogeneous and programmable compute-in-memory accelerator architecture for analog-ai using dense 2-d mesh
S Jain, H Tsai, CT Chen, R Muralidhar, I Boybat, MM Frank, S Woźniak, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (1), 114-127, 2022
422022
Neural network accelerator design with resistive crossbars: Opportunities and challenges
S Jain, A Ankit, I Chakraborty, T Gokmen, M Rasch, W Haensch, K Roy, ...
IBM Journal of Research and Development 63 (6), 10: 1-10: 13, 2019
332019
System and method for in-memory computing
S Jain, A Ranjan, K Roy, A Raghunathan
US Patent 10,073,733, 2018
332018
Non-volatile memory utilizing reconfigurable ferroelectric transistors to enable differential read and energy-efficient in-memory computation
SK Thirumala, S Jain, A Raghunathan, SK Gupta
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
282019
Computing-in-memory with spintronics
S Jain, S Sapatnekar, JP Wang, K Roy, A Raghunathan
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
272018
Approximation through logic isolation for the design of quality configurable circuits
S Jain, S Venkataramani, A Raghunathan
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 612-617, 2016
222016
Valley-coupled-spintronic non-volatile memories with compute-in-memory support
SK Thirumala, YT Hung, S Jain, A Raha, N Thakuria, V Raghunathan, ...
IEEE Transactions on Nanotechnology 19, 635-647, 2020
122020
Ternary compute-enabled memory using ferroelectric transistors for accelerating deep neural networks
SK Thirumala, S Jain, SK Gupta, A Raghunathan
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 31-36, 2020
122020
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