| Analysis of the parasitic S/D resistance in multiple-gate FETs A Dixit, A Kottantharayil, N Collaert, M Goodwin, M Jurczak, K De Meyer IEEE Transactions on Electron Devices 52 (6), 1132-1140, 2005 | 449 | 2005 |
| Multiple gate semiconductor device and method for forming same A Dixit, K De Meyer US Patent 7,202,517, 2007 | 312 | 2007 |
| Impact of line-edge roughness on FinFET matching performance E Baravelli, A Dixit, R Rooyackers, M Jurczak, NÒ Speciale, K De Meyer IEEE Transactions on Electron Devices 54 (9), 2466-2474, 2007 | 168 | 2007 |
| Multi-gate devices for the 32 nm technology node and beyond N Collaert, A De Keersgieter, A Dixit, I Ferain, LS Lai, D Lenoble, ... Solid-State Electronics 52 (9), 1291-1296, 2008 | 132 | 2008 |
| FinFET analogue characterization from DC to 110 GHz D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ... Solid-State Electronics 49 (9), 1488-1496, 2005 | 130 | 2005 |
| Impact of LER and random dopant fluctuations on FinFET matching performance E Baravelli, M Jurczak, N Speciale, K De Meyer, A Dixit IEEE transactions on nanotechnology 7 (3), 291-298, 2008 | 123 | 2008 |
| A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node N Collaert, A Dixit, M Goodwin, KG Anil, R Rooyackers, B Degroote, ... IEEE Electron Device Letters 25 (8), 568-570, 2004 | 95 | 2004 |
| A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM K von Arnim, E Augendre, C Pacha, T Schulz, KT San, F Bauer, ... 2007 IEEE symposium on VLSI technology, 106-107, 2007 | 86 | 2007 |
| 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/in the source and drain regions P Verheyen, N Collaert, R Rooyackers, R Loo, D Shamiryan, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 194-195, 2005 | 65 | 2005 |
| GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices T Hoffmann, G Doornbos, I Ferain, N Collaert, P Zimmerman, M Goodwin, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 62 | 2005 |
| Evaluation of 10-nm bulk FinFET RF performance—Conventional versus NC-FinFET R Singh, K Aditya, SS Parihar, YS Chauhan, R Vega, TB Hook, A Dixit IEEE Electron Device Letters 39 (8), 1246-1249, 2018 | 60 | 2018 |
| Modeling of effective thermal resistance in sub-14-nm stacked nanowire and FinFETs I Jain, A Gupta, TB Hook, A Dixit IEEE Transactions on Electron Devices 65 (10), 4238-4244, 2018 | 57 | 2018 |
| Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness A Dixit, KG Anil, E Baravelli, P Roussel, A Mercha, C Gustin, M Bamal, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 54 | 2006 |
| Reliability comparison of triple-gate versus planar SOI FETs F Crupi, B Kaczer, R Degraeve, V Subramanian, P Srinivasan, E Simoen, ... IEEE Transactions on electron devices 53 (9), 2351-2357, 2006 | 53 | 2006 |
| Reliability modeling and analysis of hot-carrier degradation in multiple-fin SOI n-channel FinFETs with self-heating A Gupta, C Gupta, RA Vega, TB Hook, A Dixit IEEE Transactions on Electron Devices 66 (5), 2075-2080, 2019 | 41 | 2019 |
| 3-D LER and RDF matching performance of nanowire FETs in inversion, accumulation, and junctionless modes AK Bansal, C Gupta, A Gupta, R Singh, TB Hook, A Dixit IEEE Transactions on Electron Devices 65 (3), 1246-1252, 2018 | 38 | 2018 |
| Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology AK BANSAL, I JAIN, TB HOOK, A DIXIT Journal of Electron Device Society 4 (5), 262-272, 2016 | 38 | 2016 |
| Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density B Degroote, R Rooyackers, T Vandeweyer, N Collaert, W Boullart, ... Microelectronic engineering 84 (4), 609-618, 2007 | 37 | 2007 |
| High density six transistor FinFET SRAM cell layout A Dixit US Patent 8,445,384, 2013 | 36 | 2013 |
| Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth N Collaert, R Rooyackers, A Hikavyy, A Dixit, F Leys, P Verheyen, R Loo, ... Thin Solid Films 517 (1), 101-104, 2008 | 36 | 2008 |
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