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Heiner Giefers
Heiner Giefers
South Westphalia University of Applied Sciences
Preverjeni e-poštni naslov na fh-swf.de - Domača stran
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Leto
Mixed-precision in-memory computing
M Le Gallo, A Sebastian, R Mathis, M Manica, H Giefers, T Tuma, C Bekas, ...
Nature Electronics 1 (4), 246-253, 2018
4542018
Compressed sensing with approximate message passing using in-memory computing
M Le Gallo, A Sebastian, G Cherubini, H Giefers, E Eleftheriou
IEEE Transactions on Electron Devices 65 (10), 4304-4312, 2018
1102018
Sparse matrix multiplication using a single field programmable gate array module
C Bekas, A Curioni, H Giefers, C Hagleitner, RC Polig, PWJ Staar
US Patent 9,558,156, 2017
552017
Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA
H Giefers, P Staar, C Bekas, C Hagleitner
2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016
472016
Compressed sensing recovery using computational memory
M Le Gallo, A Sebastian, G Cherubini, H Giefers, E Eleftheriou
2017 IEEE International Electron Devices Meeting (IEDM), 28.3. 1-28.3. 4, 2017
362017
Accelerating arithmetic kernels with coherent attached FPGA coprocessors
H Giefers, R Polig, C Hagleitner
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
352015
Accelerating finite difference time domain simulations with reconfigurable dataflow computers
H Giefers, C Plessl, J Förstner
ACM SIGARCH Computer Architecture News 41 (5), 65-70, 2014
292014
Sparse matrix multiplication using a single field programmable gate array module
C Bekas, A Curioni, H Giefers, C Hagleitner, RC Polig, PWJ Staar
US Patent 10,685,082, 2020
232020
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system.
H Giefers, R Polig, C Hagleitner
ASAP, 92-99, 2014
232014
A many-core implementation based on the reconfigurable mesh model
H Giefers, M Platzner
2007 International Conference on Field Programmable Logic and Applications …, 2007
232007
A triple hybrid interconnect for many-cores: Reconfigurable Mesh, NoC and barrier
H Giefers, M Platzner
2010 International Conference on Field Programmable Logic and Applications …, 2010
202010
Compiling text analytics queries to FPGAs
R Polig, K Atasu, H Giefers, L Chiticariu
2014 24th international conference on Field Programmable Logic and …, 2014
162014
ARMLang: A language and compiler for programming reconfigurable mesh many-cores
H Giefers, M Platzner
2009 IEEE International Symposium on Parallel & Distributed Processing, 1-8, 2009
152009
An FPGA-based reconfigurable mesh many-core
H Giefers, M Platzner
IEEE Transactions on Computers 63 (12), 2919-2932, 2013
142013
A fast, hybrid, power-efficient high-precision solver for large linear systems based on low-precision hardware
CM Angerer, R Polig, D Zegarac, H Giefers, C Hagleitner, C Bekas, ...
Sustainable Computing: Informatics and Systems 12, 72-82, 2016
122016
ecTALK: Energy efficient coherent transprecision accelerators—The bidirectional long short-term memory neural network case
D Diamantopoulos, H Giefers, C Hagleitner
2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2018
112018
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA
H Giefers, P Staar, R Polig
2016 26th International Conference on Field Programmable Logic and …, 2016
102016
Artificial neural network implementation in field-programmable gate arrays
D Diamantopoulos, H Giefers, C Hagleitner
US Patent 11,783,200, 2023
82023
Iterative refinement apparatus
CM Angerer, K Bekas, A Curioni, S Dragone, H Giefers, C Hagleitner, ...
US Patent 9,779,061, 2017
82017
Measuring and modeling the power consumption of energy-efficient FPGA coprocessors for GEMM and FFT
H Giefers, R Polig, C Hagleitner
Journal of Signal Processing Systems 85, 307-323, 2016
82016
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