| An optimal design of full adder based on 5-input majority gate in coplanar quantum-dot cellular automata TN Sasamal, AK Singh, A Mohan Optik 127 (20), 8576-8591, 2016 | 117 | 2016 |
| Efficient design of reversible alu in quantum-dot cellular automata TN Sasamal, AK Singh, A Mohan Optik 127 (15), 6172-6182, 2016 | 69 | 2016 |
| Design of non‐restoring binary array divider in majority logic‐based QCA TN Sasamal, AK Singh, U Ghanekar Electronics Letters 52 (24), 2001-2003, 2016 | 59 | 2016 |
| Efficient Design of Coplanar Ripple Carry Adder in QCA TN Sasamal, AK Singh, U Ghanekar IET Circuits Devices & Systems, 2018 | 57 | 2018 |
| Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates TN Sasamal, AK Singh, U Ghanekar Journal of Circuits, Systems, and Computers, 2018 | 50 | 2018 |
| An Efficient Design of Quantum-dot Cellular Automata Based 5-Input Majority Gate with Power Analysis TN Sasamal, AK Singh, A Mohan Microprocessors and Microsystems, 2018 | 48 | 2018 |
| Quantum-dot cellular automata based digital logic circuits: a design perspective TN Sasamal, AK Singh, A Mohan Springer 10, 978-981, 2020 | 46 | 2020 |
| Design of QCA-Based D Flip Flop and Memory Cell Using Rotated Majority Gate TN Sasamal, AK Singh, U Ghanekar Smart Innovations in Communication and Computational Science, Advances in …, 2018 | 46 | 2018 |
| Reversible logic circuit synthesis and optimization using adaptive genetic algorithm TN Sasamal, AK Singh, A Mohan Elsevier, Procedia Computer Science 70, 407-413, 2015 | 39 | 2015 |
| An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata A Chudasama, TN Sasamal, J Yadav Computers & Electrical Engineering 65, 527-542, 2018 | 38 | 2018 |
| Toward Efficient Design of Reversible Logic Gates in Quantum-Dot Cellular Automata with Power Dissipation Analysis TN Sasamal, AK Singh, U Ghanekar International Journal of Theoretical Physics, 2017 | 34 | 2017 |
| Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata TN Sasamal, A Mohan, AK Singh Journal of Circuits, Systems and Computers 27 (2), 2017 | 33 | 2017 |
| Efficient Design of Full Adder and Subtractor using 5-input Majority gate in QCA R Jaiswal, TN Sasamal IEEE Tenth International Conference on Contemporary Computing (IC3-2017), 2017 | 32 | 2017 |
| Implementation of 4× 4 vedic multiplier using carry save adder in quantum-dot cellular automata A Chudasama, TN Sasamal 2016 International conference on communication and signal processing (ICCSP …, 2016 | 31 | 2016 |
| Design of Cost-efficient QCA reversible circuits via Clock-Zone-Based Crossover TN Sasamal, AK Singh, A Mohan International Journal of Theoretical Physics (IJTP), 2018 | 22 | 2018 |
| An optimal design of 2-to-4 decoder in Quantum-dot Cellular Automata M Kumar, TN Sasamal Energy Procedia 117, 450-457, 2017 | 19 | 2017 |
| Design and analysis of ultra-low power QCA parity generator circuit TN Sasamal, AK Singh, U Ghanekar Springer Lecture Notes in Electrical Engineering: Proceedings of 1st ETAEERE …, 2017 | 18 | 2017 |
| Reversible logic: An introduction HM Gaur, TN Sasamal, AK Singh, A Mohan, DK Pradhan Design and Testing of Reversible Logic, 3-18, 2020 | 17 | 2020 |
| Design and synthesis of goldschmidt algorithm based floating point divider on FPGA N Singh, TN Sasamal 2016 International Conference on Communication and Signal Processing (ICCSP …, 2016 | 17 | 2016 |
| Modified positive feedback adiabatic logic for ultra low power VLSI SPS Kushawaha, TN Sasamal 2015 International Conference on Computer, Communication and Control (IC4), 1-5, 2015 | 14 | 2015 |
Prof. Ashutosh Kumar SinghProfessor and Director, Indian Institute of Information Technology, Bhopal, IndiaВерификована је имејл адреса на nitkkr.ac.in
