| A 167-processor computational platform in 65 nm CMOS DN Truong, WH Cheng, T Mohsenin, Z Yu, AT Jacobson, G Landge, ... IEEE Journal of Solid-State Circuits 44 (4), 1130-1144, 2009 | 318 | 2009 |
| An asynchronous array of simple processors for DSP applications Z Yu, M Meeuwsen, R Apperson, O Sattari, M Lai, J Webb, E Work, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 126 | 2006 |
| AsAP: An asynchronous array of simple processors Z Yu, MJ Meeuwsen, RW Apperson, O Sattari, M Lai, JW Webb, EW Work, ... IEEE Journal of Solid-State Circuits 43 (3), 695-705, 2008 | 115 | 2008 |
| A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains RW Apperson, Z Yu, MJ Meeuwsen, T Mohsenin, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (10 …, 2007 | 110 | 2007 |
| A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ... 2008 IEEE Symposium on VLSI Circuits, 22-23, 2008 | 92 | 2008 |
| High performance, energy efficiency, and scalability with GALS chip multiprocessors Z Yu, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (1), 66-79, 2008 | 55 | 2008 |
| AsAP: A fine-grained many-core platform for DSP applications B Baas, Z Yu, M Meeuwsen, O Sattari, R Apperson, E Work, J Webb, ... IEEE Micro 27 (2), 34-45, 2007 | 50 | 2007 |
| A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array P Ou, J Zhang, H Quan, Y Li, M He, Z Yu, X Yu, S Cui, J Feng, S Zhu, J Lin, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 46 | 2013 |
| A scalable network-on-chip microprocessor with 2.5 D integrated memory and accelerator SM PD, J Lin, S Zhu, Y Yin, X Liu, X Huang, C Song, W Zhang, M Yan, ... IEEE Transactions on Circuits and Systems I: Regular Papers 64 (6), 1432-1443, 2017 | 42 | 2017 |
| An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms Z Yu, K You, R Xiao, H Quan, P Ou, Y Ying, H Yang, X Zeng 2012 IEEE International Solid-State Circuits Conference, 64-66, 2012 | 42 | 2012 |
| Implementing tile-based chip multiprocessors with GALS clocking styles Z Yu, B Baas 2006 International Conference on Computer Design, 174-179, 2006 | 38 | 2006 |
| A low-area multi-link interconnect architecture for GALS chip multiprocessors Z Yu, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (5), 750-762, 2009 | 37 | 2009 |
| Parallelization of radix-2 Montgomery multiplication on multicore platform J Han, S Wang, W Huang, Z Yu, X Zeng IEEE transactions on very large scale integration (VLSI) systems 21 (12 …, 2013 | 33 | 2013 |
| Low-cost adaptive exponential integrate-and-fire neuron using stochastic computing S Xiao, W Liu, Y Guo, Z Yu IEEE Transactions on Biomedical Circuits and Systems 14 (5), 942-950, 2020 | 30 | 2020 |
| A 65 nm cryptographic processor for high speed pairing computation J Han, Y Li, Z Yu, X Zeng IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 692-701, 2014 | 30 | 2014 |
| A 68-mw 2.2 tops/w low bit width and multiplierless DCNN object detection processor for visually impaired people X Chen, J Xu, Z Yu IEEE Transactions on Circuits and Systems for Video Technology 29 (11), 3444 …, 2018 | 28 | 2018 |
| An FPGA-based hardware accelerator for traffic sign detection W Shi, X Li, Z Yu, G Overett IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2016 | 27 | 2016 |
| An optimized mapping algorithm based on simulated annealing for regular NoC architecture L Zhong, J Sheng, Z Yu, X Zeng, D Zhou 2011 9th IEEE International Conference on ASIC, 389-392, 2011 | 27 | 2011 |
| A low-power asynchronous RISC-V processor with propagated timing constraints method Z Li, Y Huang, L Tian, R Zhu, S Xiao, Z Yu IEEE Transactions on Circuits and Systems II: Express Briefs 68 (9), 3153-3157, 2021 | 23 | 2021 |
| 3D-VNPU: A flexible accelerator for 2D/3D CNNs on FPGA H Deng, J Wang, H Ye, S Xiao, X Meng, Z Yu 2021 IEEE 29th annual international symposium on field-programmable custom …, 2021 | 23 | 2021 |
