| GANA: Graph convolutional network based automated netlist annotation for analog circuits K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2020 | 86 | 2020 |
| ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 62 | 2020 |
| A general approach for identifying hierarchical symmetry constraints for analog circuit layout K Kunal, J Poojary, T Dhar, M Madhusudan, R Harjani, SS Sapatnekar Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 51 | 2020 |
| Constructive common-centroid placement and routing for binary-weighted capacitor arrays N Karmokar, AK Sharma, J Poojary, M Madhusudan, R Harjani, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 166-171, 2022 | 12 | 2022 |
| Constructive placement and routing for common-centroid capacitor arrays in binary-weighted and split DACs N Karmokar, AK Sharma, J Poojary, M Madhusudan, R Harjani, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 10 | 2023 |
| GNN-based hierarchical annotation for analog circuits K Kunal, T Dhar, M Madhusudan, J Poojary, AK Sharma, W Xu, SM Burns, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 10 | 2023 |
| Fast and efficient constraint evaluation of analog layout using machine learning models T Dhar, J Poojary, Y Li, K Kunal, M Madhusudan, AK Sharma, SD Manasi, ... Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 8 | 2021 |
| The ALIGN open-source analog layout generator: v1. 0 and beyond T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020 | 8 | 2020 |
| Machine Learning for Analog Layout SM Burns, H Chen, T Dhar, R Harjani, J Hu, N Karmokar, K Kunal, Y Li, ... Machine Learning Applications in Electronic Design Automation, 505-544, 2022 | 6 | 2022 |
| 6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB J Poojary, R Harjani 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 96-98, 2021 | 6 | 2021 |
| A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts RS Gopalakrishnan, M Madhusudan, AK Sharma, J Poojary, S Yaldiz, ... ACM Transactions on Design Automation of Electronic Systems 28 (5), 1-25, 2023 | 4 | 2023 |
| Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology M Madhusudan, J Poojary, AK Sharma, S Ramprasath, K Kunal, ... ESSDERC 2023-IEEE 53rd European Solid-State Device Research Conference …, 2023 | 3 | 2023 |
| Exploration of Design/Layout Tradeoffs for RF Circuits using ALIGN J Poojary, S Ramprasath, SS Sapatnekar, R Harjani 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 57-60, 2023 | 3 | 2023 |
| Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. S Ramprasath, M Madhusudan, AK Sharma, J Poojary, S Yaldiz, ... ISPD, 159-166, 2022 | 3 | 2022 |
| A charge flow formulation for guiding analog/mixed-signal placement T Dhar, S Ramprasath, J Poojary, S Yaldiz, S Burns, R Harjani, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 148-153, 2022 | 3 | 2022 |
| Aging of current DACs and its impact in equalizer circuits T Dhar, J Poojary, R Harjani, SS Sapatnekar 2021 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2021 | 3 | 2021 |
| An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer T Dhar, J Poojary, R Harjani, SS Sapatnekar Microelectronics Reliability 142, 114912, 2023 | 1 | 2023 |
| Reinforcing the Connection between Analog Design and EDA K Kunal, M Madhusudan, J Poojary, S Ramprasath, AK Sharma, ... 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 665-670, 2024 | | 2024 |
| Automated synthesis of mixed-signal ML inference hardware under accuracy constraints K Kunal, J Poojary, S Ramprasath, R Harjani, SS Sapatnekar 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 478-483, 2024 | | 2024 |
| High Linearity Receiver in the Presence of Blockers: Circuit Design and Layout Automation J Poojary University of Minnesota, 2023 | | 2023 |
Ramesh HarjaniE. F. Johnson Professor, Electrical & Computer Engineering, University of MinnesotaВерификована је имејл адреса на umn.edu