| Efficient Neural Network Compression H Kim, M Umar Karim Khan, CM Kyung The IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 12569 …, 2019 | 143 | 2019 |
| A high-throughput depth estimation processor for accurate semiglobal stereo matching using pipelined inter-pixel aggregation Y Lee, H Kim IEEE Transactions on Circuits and Systems for Video Technology 32 (1), 411-422, 2021 | 29 | 2021 |
| Distributed CRC architecture for high-radix parallel turbo decoding in LTE-advanced systems H Kim, I Choi, W Byun, JY Lee, JH Kim IEEE Transactions on Circuits and Systems II: Express Briefs 62 (9), 906-910, 2015 | 11 | 2015 |
| Automatic rank selection for high-speed convolutional neural network H Kim, CM Kyung arXiv preprint arXiv:1806.10821, 2018 | 9 | 2018 |
| Low‐complexity CRC‐aided early stopping unit for parallel turbo decoder H Kim, Y Lee, JH Kim Electronics Letters 51 (21), 1660-1662, 2015 | 7 | 2015 |
| Live demonstration: A neural processor for AI acceleration H Kim, J Chung, K Shin, CG Lyuh, HM Kim, C Kim, YCP Cho, J Yang, ... 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2021 | 5 | 2021 |
| Depth extraction with offset pixels WJ Yun, YG Kim, YM Lee, JY Lim, HJ Kim, MUK Khan, S Chang, HS Park, ... Optics express 26 (12), 15825-15841, 2018 | 5 | 2018 |
| M3FPU: Multiformat matrix multiplication FPU architectures for neural network computations W Jeon, YCP Cho, HM Kim, H Kim, J Chung, J Kim, M Lee, CG Lyuh, ... 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 3 | 2022 |
| Design of early stopping unit in parallel turbo decoder based on galois field operation H Kim, JH Kim International SoC Design Conference (ISOCC), 50-51, 2013 | 2 | 2013 |
| PF‐GEMV: Utilization maximizing architecture in fast matrix–vector multiplication for GPT‐2 inference H Kim, Y Lee, CG Lyuh ETRI Journal 46 (5), 817-828, 2024 | 1 | 2024 |
| Trends of Low-Precision Processing for AI Processor HJ Kim, JH Han, YS Kwon Electronics and Telecommunications Trends 37 (1), 53-62, 2022 | 1 | 2022 |
| Trends of Compiler Development for AI Processor JK Kim, HJ Kim, YCP Cho, HM Kim, CG Lyuh, J Han, Y Kwon Electronics and Telecommunications Trends 36 (2), 32-42, 2021 | 1 | 2021 |
| High throughput radix-4 SISO decoding architecture with reduced memory requirement W Byun, H Kim, JH Kim JSTS: Journal of Semiconductor Technology and Science 14 (4), 407-418, 2014 | 1 | 2014 |
| Method and apparatus for floating-point data type matrix multiplication based on outer product W Jeon, YS Kwon, JY Kim, HM Kim, H Kim, L Chun-Gi, MY Lee, JH Chung, ... US Patent App. 18/109,690, 2023 | | 2023 |
| Accuracy-aware efficient neural network compression for resource-limited system H Kim 한국과학기술원, 2020 | | 2020 |
| Apparatus and method for cyclic redundancy check H Kim, JH Kim US Patent 10,067,821, 2018 | | 2018 |
| Real-time depth map processor for offset aperture based single camera system H Kim, J Lim, Y Lee, W Yun, YG Kim, W Choi, A Khan, MUK Khan, ... 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 293-294, 2018 | | 2018 |
| Research on Distributed CRC Architecture with Galois Field Arithmetic for High-Radix Parallel Turbo Decoding H Kim Chungnam National University, 2015 | | 2015 |