| Detailed placement algorithm for VLSI design with double-row height standard cells G Wu, C Chu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 57 | 2015 |
| Flip-flop clustering by weighted K-means algorithm G Wu, Y Xu, D Wu, M Ragupathy, Y Mo, C Chu Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 34 | 2016 |
| POLAR 3.0: An ultrafast global placement engine T Lin, C Chu, G Wu 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 520-527, 2015 | 31 | 2015 |
| Flip-flop clustering for integrated circuit design Y Xu, MK Ragupathy, YY Mo, D Wu, G Wu US Patent 9,792,398, 2017 | 11 | 2017 |
| Two approaches for timing-driven placement by Lagrangian relaxation G Wu, C Chu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 11 | 2017 |
| Asynchronous circuit placement by lagrangian relaxation G Wu, T Lin, HH Huang, C Chu, PA Beerel 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 641-646, 2014 | 10 | 2014 |
| Gate sizing and Vth assignment for asynchronous circuits using Lagrangian relaxation G Wu, A Sharma, C Chu 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 4 | 2015 |
| Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits G Wu, C Chu 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 3 | 2016 |
| A fast incremental cycle ratio algorithm G Wu, C Chu Proceedings of the 2017 ACM on International Symposium on Physical Design, 75-82, 2017 | 2 | 2017 |
| Physical design algorithms for asynchronous circuits G Wu Iowa State University, 2016 | | 2016 |
