| Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain S Cadambi, A Majumdar, M Becchi, S Chakradhar, HP Graf US Patent 8,583,896, 2013 | 478 | 2013 |
| A programmable parallel accelerator for learning and classification S Cadambi, A Majumdar, M Becchi, S Chakradhar, HP Graf Proceedings of the 19th international conference on Parallel architectures …, 2010 | 140 | 2010 |
| Dynamic gpgpu power management using adaptive model predictive control A Majumdar, L Piga, I Paul, JL Greathouse, W Huang, DH Albonesi 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 59 | 2017 |
| A massively parallel, energy efficient programmable accelerator for learning and classification A Majumdar, S Cadambi, M Becchi, ST Chakradhar, HP Graf ACM Transactions on Architecture and Code Optimization (TACO) 9 (1), 1-30, 2012 | 55 | 2012 |
| Energy-comfort optimization using discomfort history and probabilistic occupancy prediction A Majumdar, JL Setter, JR Dobbs, BM Hencey, DH Albonesi International Green Computing Conference, 1-10, 2014 | 47 | 2014 |
| Energy-aware meeting scheduling algorithms for smart buildings A Majumdar, DH Albonesi, P Bose Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for …, 2012 | 39 | 2012 |
| Temperature-aware task scheduling and proactive power management A Majumdar, BJ Kocoloski, L Piga, W Huang, Y Eckert US Patent 10,452,437, 2019 | 26 | 2019 |
| An energy-efficient heterogeneous system for embedded learning and classification A Majumdar, S Cadambi, ST Chakradhar IEEE embedded systems letters 3 (1), 42-45, 2010 | 22 | 2010 |
| A taxonomy of gpgpu performance scaling A Majumdar, G Wu, K Dev, JL Greathouse, I Paul, W Huang, ... 2015 IEEE International Symposium on Workload Characterization, 118-119, 2015 | 20 | 2015 |
| Energy efficient heterogeneous systems A Majumdar, S Cadambi, ST Chakradhar US Patent 8,874,943, 2014 | 19 | 2014 |
| Real-time performance tracking using dynamic compilation L Piga, BJ Kocoloski, W Huang, A Majumdar, I Paul US Patent App. 15/192,748, 2017 | 13 | 2017 |
| Characterizing the benefits and limitations of smart building meeting room scheduling A Majumdar, Z Zhang, DH Albonesi 2016 ACM/IEEE 7th International Conference on Cyber-Physical Systems (ICCPS …, 2016 | 13 | 2016 |
| A research retrospective on amd's exascale computing journey GH Loh, MJ Schulte, M Ignatowski, V Adhinarayanan, S Aga, D Aguren, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 10 | 2023 |
| 128-bit AES decryption S Bhargav, L Chen, A Majumdar, S Ramudit Project report, CSEE, 2008 | 6 | 2008 |
| A parallel accelerator for semantic search A Majumdar, S Cadambi, ST Chakradhar, HP Graf 2011 IEEE 9th Symposium on Application Specific Processors (SASP), 122-128, 2011 | 3 | 2011 |
| FPGA Implementation Of Integer Linear Programming Accelerator A Majumdar International Conference on Systemics, Cybernetics and Informatics,(ICSCI), 2006 | 3 | 2006 |
| Hardware accuracy counters for application precision and quality feedback LPR Piga, A Majumdar, I Paul, W Huang, M Arora, JL Greathouse US Patent 9,990,203, 2018 | 2 | 2018 |
| FPGA-based 128-bit AES decryption S Bhargav, L Chen, A Majumdar, S Ramudit CSEE, 2008 | 2 | 2008 |
| Method and apparatus for managing power in a thermal couple aware system W Huang, M Arora, A Majumdar, I Paul, LPR Piga US Patent 10,955,884, 2021 | | 2021 |
| Hardware accuracy counters for application precision and quality feedback L de Paula Rosa Piga, A Majumdar, I Paul, W Huang, M Arora, ... Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States), 2018 | | 2018 |
Srihari CadambiNEC Laboratories America, Inc.Верификована је имејл адреса на nec-labs.com
