| An asynchronous NOC architecture providing low latency service and its multi-level design framework E Beigné, F Clermidy, P Vivet, A Clouard, M Renaudin 11th IEEE International Symposium on Asynchronous Circuits and Systems, 54-63, 2005 | 350 | 2005 |
| Spiking neural networks hardware implementations and challenges: A survey M Bouvier, A Valentian, T Mesquida, F Rummens, M Reyboz, E Vianello, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 15 (2), 1-35, 2019 | 303 | 2019 |
| Globally asynchronous communication architecture for system on chip F Clermidy, P Vivet, E Beigne US Patent 7,957,381, 2011 | 299 | 2011 |
| An asynchronous power aware and adaptive NoC based circuit E Beigné, F Clermidy, H Lhermet, S Miermont, Y Thonnart, XT Tran, ... IEEE Journal of solid-state Circuits 44 (4), 1167-1177, 2009 | 165 | 2009 |
| Design of on-chip and off-chip interfaces for a GALS NoC architecture E Beigné, P Vivet 12th IEEE International Symposium on Asynchronous Circuits and Systems …, 2006 | 135 | 2006 |
| Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC E Beigne, F Clermidy, S Miermont, P Vivet Proceedings of the Second ACM/IEEE International Symposium on Networks-on …, 2008 | 122 | 2008 |
| A reconfigurable baseband platform based on an asynchronous network-on-chip D Lattard, E Beigne, F Clermidy, Y Durand, R Lemaire, P Vivet, F Berens IEEE Journal of Solid-State Circuits 43 (1), 223-235, 2008 | 119 | 2008 |
| AES datapath optimization strategies for low-power low-energy multisecurity-level internet-of-things applications DH Bui, D Puschini, S Bacles-Min, E Beigné, XT Tran IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 102 | 2017 |
| A telecom baseband circuit based on an asynchronous network-on-chip D Lattard, E Beigne, C Bernard, C Bour, F Clermidy, Y Durand, J Durupt, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 90 | 2007 |
| Resistive RAM endurance: Array-level characterization and correction techniques targeting deep learning applications A Grossi, E Vianello, MM Sabry, M Barlas, L Grenouillet, J Coignus, ... IEEE Transactions on Electron Devices 66 (3), 1281-1288, 2019 | 79 | 2019 |
| Energy-efficient near-threshold parallel computing: The PULPv2 cluster D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ... Ieee Micro 37 (5), 20-31, 2017 | 75 | 2017 |
| Resistive RAM with multiple bits per cell: Array-level demonstration of 3 bits per cell BQ Le, A Grossi, E Vianello, T Wu, G Lama, E Beigne, HSP Wong, S Mitra IEEE Transactions on Electron Devices 66 (1), 641-646, 2018 | 72 | 2018 |
| Design and implementation of a GALS adapter for ANoC based architectures Y Thonnart, E Beigné, P Vivet 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 13-22, 2009 | 65 | 2009 |
| A Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links P Vivet, Y Thonnart, R Lemaire, C Santos, E Beigné, C Bernard, F Darve, ... IEEE Journal of Solid-State Circuits 52 (1), 33-49, 2016 | 62 | 2016 |
| A 5500-frames/s 85-gops/w 3-d stacked bsi vision chip based on parallel in-focal-plane acquisition and processing L Millet, S Chevobbe, C Andriamisaina, L Benaissa, E Deschaseaux, ... IEEE Journal of Solid-State Circuits 54 (4), 1096-1105, 2019 | 60 | 2019 |
| A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ... IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014 | 58 | 2014 |
| A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 52 | 2014 |
| A pseudo-synchronous implementation flow for WCHB QDI asynchronous circuits Y Thonnart, E Beigné, P Vivet 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012 | 51 | 2012 |
| 193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ... Low-Power and High-Speed Chips (COOL CHIPS XIX), 2016 IEEE Symposium in, 1-3, 2016 | 45 | 2016 |
| Bringing robustness and power efficiency to autonomous energy harvesting microsystems JF Christmann, E Beigne, C Condemine, N Leblond, P Vivet, ... 2010 IEEE Symposium on Asynchronous Circuits and Systems, 62-71, 2010 | 40 | 2010 |
