| Tas: ternarized neural architecture search for resource-constrained edge devices M Loni, H Mousavi, M Riazati, M Daneshtalab, M Sjödin 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 29 | 2022 |
| Deepaxe: A framework for exploration of approximation and reliability trade-offs in dnn accelerators M Taheri, M Riazati, MH Ahmadilivani, M Jenihhin, M Daneshtalab, J Raik, ... 2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023 | 23 | 2023 |
| Enhancing the testability of RTL designs using efficiently synthesized assertions MR Kakoee, M Riazati, S Mohammadi 9th International Symposium on Quality Electronic Design (isqed 2008), 230-235, 2008 | 18 | 2008 |
| Distributing congestions in nocs through a dynamic routing algorithm based on input and output selections M Daneshtalab, A Pedram, MH Neishaburi, M Riazati, A Afzali-Kusha, ... 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 17 | 2007 |
| Deephls: A complete toolchain for automatic synthesis of deep neural networks to fpga M Riazati, M Daneshtalab, M Sjödin, B Lisper 2020 27th IEEE international conference on electronics, circuits and systems …, 2020 | 13 | 2020 |
| Improved assertion lifetime via assertion-based testing methodology M Riazati, S Mohammadi, A Afzali-Kusha, Z Navabi 2006 International Conference on Microelectronics, 48-51, 2006 | 7 | 2006 |
| Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification MR Kakoee, M Riazati, S Mohammadi 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | 6 | 2008 |
| Autodeephls: Deep neural network high-level synthesis using fixed-point precision M Riazati, M Daneshtalab, M Sjödin, B Lisper 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 3 | 2022 |
| Non-overlapping Set of Efficient Assertions M Riazati, S Mohammadi, Z Navabi 2006 NORCHIP, 201-204, 2006 | 3 | 2006 |
| Low-power multiplier with static decision for input manipulation M Riazati, A Sobhani, M Mottaghi-Dastjerdi, A Afzali-Kusha, A Khakifirooz 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-2724, 2006 | 3 | 2006 |
| DeepFlexiHLS: Deep neural network flexible high-level synthesis directive generator M Riazati, M Daneshtalab, M Sjödin, B Lisper 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), 1-6, 2022 | 1 | 2022 |
| Adjustable self-healing methodology for accelerated functions in heterogeneous systems M Riazati, T Ghasempouri, M Daneshtalab, J Raik, M Sjödin, B Lisper 2020 23rd Euromicro Conference on Digital System Design (DSD), 638-645, 2020 | 1 | 2020 |
| DeepKit: A Multistage Exploration Framework for Hardware Implementation of Deep Learning M Riazati PQDT-Global, 2023 | | 2023 |
| Reliability and Performance in Heterogeneous Systems Generated by High-Level Synthesis M Riazati Mälardalen University, 2021 | | 2021 |
| High-Level Synthesis Design Space Exploration for Highly Optimized Deep Neural Network Implementation M Riazati, M Daneshtalab, M Sjödin, B Lisper | | 2021 |
| SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level Designs M Riazati, M Daneshtalab, M Sjödin, B Lisper 2020 23rd International Symposium on Design and Diagnostics of Electronic …, 2020 | | 2020 |
| Finding low activity op-code sets using genetic computing M Dastjerdi-Mottaghi, M Riazati, M Daneshtalab, Z Navabi 2006 International Conference on Microelectronics, 52-57, 2006 | | 2006 |
| Assertion Efficiency Assessment Method M Riazati, S Mohammadi, Z Navabi Digest of Papers of 7th Workshop on RTL and High Level Testing, 2006 | | 2006 |