| A portable digitally controlled oscillator using novel varactors PL Chen, CC Chung, CY Lee IEEE Transactions on Circuits and Systems II: Express Briefs 52 (5), 233-237, 2005 | 150 | 2005 |
| A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications PL Chen, CC Chung, JN Yang, CY Lee IEEE Journal of Solid-State Circuits 41 (6), 1275-1285, 2006 | 73 | 2006 |
| An all-digital delay-locked loop for DDR SDRAM controller applications CC Chung, PL Chen, CY Lee 2006 International Symposium on VLSI Design, Automation and Test, 1-4, 2006 | 28 | 2006 |
| A reconfigurable TAF-DPS frequency synthesizer on FPGA achieving 2 ppb frequency granularity and two-cycle switching speed L Xiu, PL Chen IEEE Transactions on Industrial Electronics 64 (2), 1233-1240, 2016 | 21 | 2016 |
| An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications PL Chen, CC Chung, CY Lee 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 4875-4878, 2005 | 12 | 2005 |
| Phase frequency detector with a narrow control pulse CY Lee, PL Chen US Patent 6,831,485, 2004 | 7 | 2004 |
| A novel digitally-controlled varactor for portable delay cell design PL CHEN, CC CHUNG, CY Lee IEICE transactions on fundamentals of electronics, communications and …, 2004 | 6 | 2004 |
| An Interpolated Flying‐Adder‐Based Frequency Synthesizer PL Chen, CC Tsai Journal of Electrical and Computer Engineering 2011 (1), 871385, 2011 | 5 | 2011 |
| A Fully Synthesizable Ultra- Audio Frequency Multiplier for HDMI Applications PL Chen IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2134-2138, 2019 | 2 | 2019 |
| A low-cost carry look-ahead adder for flying-adder frequency synthesizer PL Chen 2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 1-2, 2016 | 2 | 2016 |
| Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method PL Chen, DC Lee, WC Li IEICE Transactions on Electronics 98 (6), 480-488, 2015 | 2 | 2015 |
| A low power multiphase all-digital phase locked loop with reusing SAR PL Chen The 2010 International Conference on Green Circuits and Systems, 695-698, 2010 | 2 | 2010 |
| A standard cell-based frequency synthesizer with dynamic frequency counting PL Chen, CY Lee IEICE transactions on fundamentals of electronics, communications and …, 2005 | 2 | 2005 |
| An all-digital clock generator with modified dynamic frequency counting loop and LFSR dithering PL Chen 2019 International Symposium on Intelligent Signal Processing and …, 2019 | 1 | 2019 |
| An Inductorless Chua's Circuit with Memristor PL Chen 2015 2nd International Conference on Information Science and Control …, 2015 | 1 | 2015 |
| A fractional pseudo random binary sequence for spur reduction in flying-adder frequency synthesizer PL Chen, CH Cheng 2014 International Conference on Information Science, Electronics and …, 2014 | 1 | 2014 |
| A jumping algorithm for calibration in multiphase delay locked loop PL Chen 2013 10th IEEE International Conference on Control and Automation (ICCA …, 2013 | 1 | 2013 |
| A multiphase all-digital delay-locked loop with reuse SAR PL Chen, TS Wang, JH Ciou 2010 IEEE Asia Pacific Conference on Circuits and Systems, 943-946, 2010 | 1 | 2010 |
| Architecture of method for fetching microprocessor's instructions PL Chen, CY Lee US Patent App. 10/024,844, 2002 | 1 | 2002 |
| A Cost-Effective TAF-DPS Syntonization Scheme of Improving Clock Frequency Accuracy and Long-Term Frequency Stability for Universal Applications L Xiu, PL Chen, Y Han Low Power Circuits for Emerging Applications in Communications, Computing …, 2018 | | 2018 |
