| A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS X Meng, J Guo, H Li, J Yin, PI Mak, RP Martins 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 11 | 2021 |
| 10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a … H Li, T Xu, X Meng, J Yin, RP Martins, PI Mak 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 204-206, 2024 | 7 | 2024 |
| Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art S Yang, J Yin, Y Liu, Z Zhu, R Bao, J Lin, H Li, Q Li, PI Mak, RP Martins Chip 2 (2), 100051, 2023 | 4 | 2023 |
| Analysis and design of a 15.2-to-18.2-GHz inverse-class-F VCO with a balanced dual-core topology suppressing the flicker noise upconversion X Meng, H Li, P Chen, J Yin, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 70 (12), 5110-5123, 2023 | 2 | 2023 |
| Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction T Xu, H Li, X Meng, X Zhan, Y Peng, J Yin, S Yang, C Fan, Z Huang, ... IEEE Transactions on Circuits and Systems II: Express Briefs, 2025 | | 2025 |
| A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment H Li, T Xu, X Meng, J Yin, RP Martins, PI Mak IEEE Journal of Solid-State Circuits, 2024 | | 2024 |