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Diya Joseph
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TCOR: A Tile Cache with Optimal Replacement
D Joseph, JL Aragón, JM Parcerisa, A González
2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022
102022
An exercise on hardware/software codesign following the RISC model
D Joseph, G Kaur, P Chakraborty
Computer Applications in Engineering Education 24 (2), 305-312, 2016
62016
DTexL: Decoupled Raster Pipeline for Texture Locality
D Joseph, JL Aragón, JM Parcerisa, A González
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 213-227, 2022
42022
WaSP: Warp Scheduling to Mimic Prefetching in Graphics Workloads
D Joseph, JL Aragón, JM Parcerisa, A Gonzalez
arXiv preprint arXiv:2404.06156, 2024
22024
Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs
D Joseph, JL Aragón, JM Parcerisa, A González
2023 32nd International Conference on Parallel Architectures and Compilation …, 2023
22023
Microarchitectural simulator for shader cores in a modern GPU simulation infrastructure
D Joseph
Universitat Politècnica de Catalunya, 2019
12019
A multipurpose toolkit for teaching DSP in an undergraduate course
D Joseph, P Chawla, H Chander, TK Rawat
Computer Applications in Engineering Education 25 (3), 530-541, 2017
12017
Liang, Shuhao 297
P Abad, ME Acacio, A Agrawal, GG Akbulut, E Aliaj, M Almasri, J An, ...
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