| A detailed and flexible cycle-accurate network-on-chip simulator N Jiang, DU Becker, G Michelogiannakis, J Balfour, B Towles, DE Shaw, ... Performance Analysis of Systems and Software (ISPASS), 2013 IEEE …, 2013 | 914 | 2013 |
| EFFICIENT MICROARCHITECTURE FOR NETWORK-ON-CHIP ROUTERS DU Becker STANFORD UNIVERSITY, 2012 | 195 | 2012 |
| Allocator implementations for network-on-chip routers DU Becker, WJ Dally High Performance Computing Networking, Storage and Analysis, Proceedings of …, 2009 | 117 | 2009 |
| Booksim 2.0 User’s Guide N Jiang, G Michelogiannakis, D Becker, B Towles, WJ Dally Stanford University, 2010 | 80 | 2010 |
| Network congestion avoidance through Speculative Reservation N Jiang, DU Becker, G Michelogiannakis, WJ Dally High Performance Computer Architecture (HPCA), 2012 IEEE 18th International …, 2012 | 78 | 2012 |
| Packet chaining: Efficient single-cycle allocation for on-chip networks G Michelogiannakis, N Jiang, D Becker, WJ Dally Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 57 | 2011 |
| Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks DU Becker, N Jiang, G Michelogiannakis, WJ Dally Proceedings of the 30th IEEE International Conference on Computer Design …, 2012 | 42 | 2012 |
| Channel reservation protocol for over-subscribed channels and destinations G Michelogiannakis, N Jiang, D Becker, WJ Dally High Performance Computing, Networking, Storage and Analysis (SC), 2013 …, 2013 | 30 | 2013 |
| Booksim interconnection network simulator N Jiang, G Michelogiannakis, D Becker, B Towles, W Dally Online, https://nocs. stanford. edu/cgi-bin/trac. cgi/wiki/Resources/BookSim, 0 | 30* | |
| Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures H Blume, T von Sydow, D Becker, TG Noll Journal of Systems Architecture 53 (8), 466-476, 2007 | 24 | 2007 |
| Evaluating elastic buffer and wormhole flow control G Michelogiannakis, D Becker, W Dally IEEE Transactions on Computers 60 (6), 896-903, 2011 | 20 | 2011 |
| Modeling noc architectures by means of deterministic and stochastic petri nets H Blume, T von Sydow, D Becker, TG Noll International Workshop on Embedded Computer Systems, 374-383, 2005 | 5 | 2005 |
| Instruction compounding for embedded microprocessors DU Becker, DB Sheffield, V Parikh Class project, 2008 | 1 | 2008 |
| Error Detection Using Gate-Level Assertions DU Becker, H Baba | | |
| Modellierung von Networks-on-Chip mit Hilfe von Deterministischen und Stochastischen Petri-Netzen D Becker | | |
William DallyChief Scientist, NVIDIA; Adjunct Professor of CS and EE, Stanford University;Verifierad e-postadress på stanford.edu
