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Emre Ozer
Emre Ozer
Pragmatic
Verifierad e-postadress på pragmaticsemi.com
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Managing cache coherency in a data processing apparatus
E Özer, SD Biles, SA Ford
US Patent 7,937,535, 2011
4602011
Scale-out processors
P Lotfi-Kamran, B Grot, M Ferdman, S Volos, O Kocberber, J Picorel, ...
ACM SIGARCH Computer Architecture News 40 (3), 500-511, 2012
2802012
A natively flexible 32-bit Arm microprocessor
J Biggs, J Myers, J Kufel, E Ozer, S Craske, A Sou, C Ramsdale, ...
Nature 595 (7868), 532-536, 2021
2362021
Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures
E Ozer, S Banerjia, TM Conte
Proceedings. 31st Annual ACM/IEEE International Symposium on …, 1998
2281998
Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction
YP Raykov, E Ozer, G Dasika, A Boukouvalas, MA Little
Proceedings of the 2016 ACM international joint conference on pervasive and …, 2016
1632016
A hardwired machine learning processing engine fabricated with submicron metal-oxide thin-film transistors on a flexible substrate
E Ozer, J Kufel, J Myers, J Biggs, G Brown, A Rana, A Sou, C Ramsdale, ...
Nature Electronics 3 (7), 419-425, 2020
992020
Cache miss detection in a data processing apparatus
M Ghosh, E Özer, SD Biles
US Patent 8,099,556, 2012
842012
A triple core lock-step (tcls) arm® cortex®-r5 processor for safety-critical and ultra-reliable applications
X Iturbe, B Venu, E Ozer, S Das
2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016
832016
Contention management for a hardware transactional memory
G Blake, TN Mudge, SD Biles, NYS Chong, E Ozer, RG Dreslinski
US Patent App. 12/292,565, 2009
822009
Multiple thread instruction fetch from different cache levels
E Özer, SD Biles
US Patent 7,769,955, 2010
772010
Real-time room occupancy estimation with Bayesian machine learning using a single PIR sensor and microcontroller
C Leech, YP Raykov, E Ozer, GV Merrett
2017 IEEE Sensors Applications Symposium (SAS), 1-6, 2017
662017
Powering a microprocessor by photosynthesis
P Bombelli, A Savanth, A Scarampi, SJL Rowden, DH Green, A Erbe, ...
Energy & Environmental Science 15 (6), 2529-2536, 2022
632022
The HiPEAC Vision 2019
M Duranton, K De Bosschere, B Coppens, C Gamrat, M Gray, H Munk, ...
HiPEAC CSA, 2019
632019
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU
X Iturbe, B Venu, E Ozer
2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2016
592016
The Arm triple core lock-step (TCLS) processor
X Iturbe, B Venu, E Ozer, JL Poupat, G Gimenez, HU Zurek
ACM Transactions on Computer Systems (TOCS) 36 (3), 1-30, 2019
572019
Estimating a number of occupants in a region
YP Raykov, E Özer, GS Dasika
US Patent 10,607,147, 2020
542020
Multiple-valued logic buses for reducing bus energy in low-power systems
E Ozer, R Sendag, D Gregg
IEE Proceedings-Computers and Digital Techniques 153 (4), 270-282, 2006
502006
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches
M Ghosh, E Ozer, S Ford, S Biles, HHS Lee
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
482009
An analytical framework for estimating tco and exploring data center design space
D Hardy, M Kleanthous, I Sideris, AG Saidi, E Ozer, Y Sazeides
2013 IEEE International Symposium on Performance Analysis of Systems and …, 2013
442013
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture
X Iturbe, B Venu, J Jagst, E Ozer, P Harrod, C Turner, J Penton
IEEE Design & Test 35 (3), 7-14, 2018
402018
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Artiklar 1–20