| ZigZag: Enlarging joint architecture-mapping design space exploration for DNN accelerators L Mei, P Houshmand, V Jain, S Giraldo, M Verhelst IEEE Transactions on Computers 70 (8), 1160-1174, 2021 | 157* | 2021 |
| DIANA: An end-to-end energy-efficient digital and ANAlog hybrid neural network SoC K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 71 | 2022 |
| Diana: An end-to-end hybrid digital and analog neural network soc for the edge P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ... IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022 | 49 | 2022 |
| Opportunities and limitations of emerging analog in-memory compute DNN architectures P Houshmand, S Cosemans, L Mei, I Papistas, D Bhattacharjee, ... 2020 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2020 | 32 | 2020 |
| Benchmarking and modeling of analog and digital SRAM in-memory computing architectures P Houshmand, J Sun, M Verhelst arXiv preprint arXiv:2305.18335, 2023 | 13 | 2023 |
| Towards heterogeneous multi-core accelerators exploiting fine-grained scheduling of layer-fused deep neural networks A Symons, L Mei, S Colleman, P Houshmand, S Karl, M Verhelst arXiv preprint arXiv:2212.10612, 2022 | 13 | 2022 |
| Hardware-efficient residual neural network execution in line-buffer depth-first processing M Shi, P Houshmand, L Mei, M Verhelst IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (4 …, 2021 | 10 | 2021 |
| Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling J Sun, P Houshmand, M Verhelst 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 9 | 2023 |
| Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators A Symons, L Mei, S Colleman, P Houshmand, S Karl, M Verhelst 2023 IEEE International Symposium on Performance Analysis of Systems and …, 2023 | 7 | 2023 |
| Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge J Dumoulin, P Houshmand, V Jain, M Verhelst 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | 2 | 2024 |
| A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W W Jiang, P Houshmand, M Verhelst, W Dehaene ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023 | 2 | 2023 |
| Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators A Symons, L Mei, S Colleman, P Houshmand, S Karl, M Verhelst IEEE Transactions on Computers, 2024 | 1 | 2024 |
| Hardware Modeling and Exploration Towards Edge AI Acceleration P Houshmand, M Verhelst | | 2025 |
| Pack my weights and run! Minimizing overheads for in-memory computing accelerators P Houshmand, M Verhelst arXiv preprint arXiv:2409.11437, 2024 | | 2024 |
| High-Rate. Compact In-Sensor Denoising for Active Stereo Vision Towards Embedded Depth Sensing P Houshmand, JS Staelens, W Van der Tempel, M Verhelst 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), 11-15, 2024 | | 2024 |
| Towards the next generation Heterogeneous Multi-core Multi-accelerator Architectures for Machine Learning V Jain, G Sarda, P Houshmand, M Verhelst Spring 2022 RISC-V Week, Location: Paris, France, 2022 | | 2022 |