| Methodology for analysis of TSV stress induced transistor variation and circuit performance L Yu, WY Chang, K Zuo, J Wang, D Yu, D Boning Thirteenth International Symposium on Quality Electronic Design (ISQED), 216-222, 2012 | 25 | 2012 |
| Statistical library characterization using belief propagation across multiple technology nodes L Yu, S Saxena, C Hess, IAM Elfadel, D Antoniadis, D Boning 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 20 | 2015 |
| Remembrance of transistors past: Compact model parameter extraction using Bayesian inference and incomplete new measurements L Yu, S Saxena, C Hess, A Elfadel, D Antoniadis, D Boning Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 20 | 2014 |
| Statistical modeling with the virtual source MOSFET model L Yu, L Wei, D Antoniadis, I Elfadel, D Boning 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 16 | 2013 |
| Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation L Yu DATE, 1-6, 2014 | 15* | 2014 |
| High-yield large area MoS2 technology: Material, device and circuits co-optimization L Yu, D El-Damak, U Radhakrishna, A Zubair, D Piedra, X Ling, Y Lin, ... 2016 IEEE International Electron Devices Meeting (IEDM), 5.7. 1-5.7. 4, 2016 | 13 | 2016 |
| An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits L Yu, O Mysore, L Wei, L Daniel, D Antoniadis, I Elfadel, D Boning 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 521-526, 2013 | 9 | 2013 |
| A study of through-silicon-via (TSV) induced transistor variation L Yu Massachusetts Institute of Technology, 2011 | 7 | 2011 |
| Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection L Yu, S Saxena, C Hess, AM Elfadel, D Antoniadis, D Boning Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 0 | 7* | |
| NA d. Braga, RV Mickevicius, and T. Palacios Y Zhang, M Sun, HY Wong, Y Lin, P Srivastava, C Hatem, M Azize, ... IEEE Trans. Electron Devices 62, 2155, 2015 | 6 | 2015 |
| Efficient IC statistical modeling and extraction using a Bayesian inference framework L Yu Massachusetts Institute of Technology, 2015 | 2 | 2015 |
| A concisely asymmetric modeling of double-π equivalent circuit for on-chip spiral inductors L Yu, Y Tang, Y Wang Solid-state electronics 54 (4), 343-348, 2010 | 2 | 2010 |
| Remembrance of Transistors Past L Yu, S Saxena, C Hess, A Elfadel, D Antoniadis, D Boning ACM Press, 2014 | | 2014 |
| On-chip spiral inductors synthesis by moving leastsquares approximation Y Li, T Yang, W Yan 2009 IEEE 8th International Conference on ASIC, 678-681, 2009 | | 2009 |
| Design, Modeling, and Fabrication of Chemical Vapor Deposition-Grown MoS2 Circuits with E-Mode Field-Effect Transistors for Large-Area Electronics L Yu, D El-Damak, S Ha, X Ling, U Radhakrishna, J Kong, ... Circuits and Systems for Information Processing, Multimedia, Communication …, 0 | | |
| Ibrahim (Abe) M. Elfadel, Dimitri Antoniadis, and Duane Boning. 2015. Statistical library characterization using belief propagation across multiple technology nodes L Yu, S Saxena, C Hess Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 0 | | |
| Efficient Device and Integrated Circuit Statistical Modeling and Extraction Using a Bayesian Inference Framework L Yu, I Elfadel, DA Antoniadis, DS Boning Electronic Devices: Transistors; Memory, Magnetic, and Superconducting …, 0 | | |
| An Efficient Bayesian Framework for Accurate Parameter Extraction from Limited Measurements L Yu, DA Antoniadis, DS Boning Electronic Devices: Transistors in Si, SiGe, Ge, III-Vs, GaN, and 2D …, 0 | | |
Duane BoningMassachusetts Institute of TechnologyVerifierad e-postadress på mtl.mit.edu
