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Laurin Luca
Laurin Luca
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Apparatuses and methods for use in selecting or isolating memory cells
L Laurin, A Benvenuti, M Riva
US Patent App. 14/077,726, 2014
442014
Impact of the current density increase on reliability in scaled BJT-selected PCM for high-density applications
A Redaelli, A Pirovano, I Tortorelli, F Ottogalli, A Ghetti, L Laurin, ...
2010 IEEE International Reliability Physics Symposium, 615-619, 2010
242010
Advanced Metrics for Quantification of By‐Process Segregation beyond Ternary Systems
E Petroni, M Patelmo, A Serafini, D Codegoni, L Laurin, M Baldo, ...
physica status solidi (RRL)–Rapid Research Letters 17 (8), 2200458, 2023
62023
Unveiling retention physical mechanism of Ge-rich GST ePCM technology
L Laurin, M Baldo, E Petroni, G Samanni, L Turconi, A Motta, M Borghi, ...
2023 IEEE International Reliability Physics Symposium (IRPS), 1-7, 2023
52023
Methods of forming microelectronic devices and memory devices, and related microelectronic devices, memory devices, and electronic systems
UM Meotto, E Camerlenghi, P Tessariol, L Laurin
US Patent 11,417,676, 2022
52022
Microelectronic devices, memory devices, and electronic systems
UM Meotto, E Camerlenghi, P Tessariol, L Laurin
US Patent 11,818,893, 2023
42023
Modeling environment for Ge-rich GST phase change memory cells
M Baldo, L Laurin, E Petroni, G Samanni, M Allegra, E Gomiero, D Ielmini, ...
2022 IEEE International Memory Workshop (IMW), 1-4, 2022
32022
Sequential voltage ramp-down of access lines of non-volatile memory device
A Fayrushin, A Benvenuti, A Goda, L Laurin, H Liu
US Patent 10,803,948, 2020
32020
Modeling and analysis of virgin Ge-rich GST embedded phase change memories
M Baldo, O Melnic, M Scudieri, G Nicotra, M Borghi, E Petroni, A Motta, ...
IEEE Transactions on Electron Devices 70 (3), 1055-1060, 2023
22023
Characterization of reset state through energy activation study in Ge-GST based ePCM
M Baldo, L Turconi, A Motta, E Petroni, L Laurin, D Ielmini, A Redaelli
ESSDERC 2022-IEEE 52nd European Solid-State Device Research Conference …, 2022
22022
Integrated assemblies having transistors configured for high-voltage applications
ZA Shafi, L Laurin, DP Panda, S Vigano
US Patent 11,430,888, 2022
22022
Interaction between forming pulse and integration process flow in ePCM
M Baldo, E Petroni, L Laurin, G Samanni, O Melnic, D Ielmini, A Redaelli
2022 17th Conference on Ph. D Research in Microelectronics and Electronics …, 2022
22022
Atomistic approach for Boron Transient enhanced diffusion and clustering
A Mauri, L Laurin, F Montalenti, A Benvenuti
2008 International Conference on Simulation of Semiconductor Processes and …, 2008
22008
Study of Ge‐Rich Ge–Sb–Te Device‐Dependent Segregation for Industrial Grade Embedded Phase‐Change Memory
E Petroni, M Allegra, M Baldo, L Laurin, A Serafini, L Favennec, ...
physica status solidi (RRL)–Rapid Research Letters 18 (10), 2300449, 2024
12024
Sequential voltage ramp-down of access lines of non-volatile memory device
A Fayrushin, A Benvenuti, A Goda, L Laurin, H Liu
US Patent 11,417,396, 2022
12022
High Ion/Ioff ratio BJT selector for 32 cell string resistive RAM arrays
A Redaelli, L Laurin, S Lavizzari, C Cupeta, G Servalli, A Benvenuti
2014 44th European Solid State Device Research Conference (ESSDERC), 238-241, 2014
12014
Bipolar junction transistors and memory arrays
F Ottogalli, L Laurin
US Patent 8,766,235, 2014
12014
The role of the substrate in the high energy boron implantation damage recovering
I Mica, L Di Piazza, L Laurin, M Mariani, AG Mauri, ML Polignano, E Ricci, ...
Materials Science and Engineering: B 159, 168-172, 2009
12009
PROCESS FOR COINTEGRATION OF TWO PHASE CHANGE MEMORY (PCM) ARRAYS HAVING DIFFERENT PHASE CHANGE MATERIALS, AND IN-MEMORY COMPUTATION SYSTEM UTILIZING THE TWO PCM ARRAYS
A Redaelli, L Laurin
US Patent App. 18/228,736, 2025
2025
Memory devices
UM Meotto, E Camerlenghi, P Tessariol, L Laurin
US Patent 12,207,473, 2025
2025
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