ติดตาม
Jose Monteiro
Jose Monteiro
INESC-ID, Instituto Superior Técnico - U Lisboa
ยืนยันอีเมลแล้วที่ inesc-id.pt - หน้าแรก
ชื่อ
อ้างโดย
อ้างโดย
ปี
Precomputation-based sequential logic optimization for low power
M Alidina, J Monteiro, S Devadas, A Ghosh, M Papaefthymiou
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (4), 426-436, 1994
486*1994
Retiming sequential circuits for low power
J Monteiro, S Devadas, A Ghosh
International journal of high speed electronics and systems 7 (02), 323-340, 1996
2771996
Power estimation methods for sequential logic circuits
CY Tsui, J Monteiro, M Pedram, S Devadas, AM Despain, B Lin
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (3), 404-416, 1995
2111995
A methodology for efficient estimation of switching activity in sequential logic circuits
J Monteiro, S Devadas, B Lin
Proceedings of the 31st annual Design Automation Conference, 12-17, 1994
1781994
Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications
L Aksoy, E Da Costa, P Flores, J Monteiro
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
1682008
Scheduling techniques to enable power management
J Monteiro, S Devadas, P Ashar, A Mauskar
Proceedings of the 33rd annual Design Automation Conference, 349-352, 1996
1541996
Estimation of average switching activity in combinational logic circuits using symbolic simulation
J Monteiro, S Devadas, A Ghosh, K Keutzer, J White
IEEE transactions on computer-aided design of integrated circuits and …, 1997
1201997
Finite state machine decomposition for low power
JC Monteiro, AL Oliveira
Proceedings of the 35th annual Design Automation Conference, 758-763, 1998
1181998
Switching activity estimation using limited depth reconvergent path analysis
JC Costa, JC Monteiro, S Devadas
Proceedings of the 1997 international symposium on Low power electronics and …, 1997
831997
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
P Flores, J Monteiro, E Costa
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
802005
Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation
P Flores, J Costa, H Neto, J Monteiro, J Marques-Silva
Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999
691999
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11 …
J Monteiro, R Van Leuken
Springer Science & Business Media, 2010
642010
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
J Monteiro, S Devadas
Springer Science & Business Media, 2012
562012
Design of digit-serial FIR filters: Algorithms, architectures, and a CAD tool
L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro
IEEE transactions on very large Scale integration (VLSI) systems 21 (3), 498-511, 2012
562012
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
J Monteiro, S Devadas
Proceedings of the 1995 international symposium on Low power design, 33-38, 1995
541995
Optimization of area in digital FIR filters using gate-level metrics
L Aksov, E Costa, P Flores, J Monteiro
Proceedings of the 44th annual Design Automation Conference, 420-423, 2007
532007
A review of synthetic-aperture radar image formation algorithms and implementations: A computational perspective
H Cruz, M Véstias, J Monteiro, H Neto, RP Duarte
Remote Sensing 14 (5), 1258, 2022
522022
A tutorial on multiplierless design of FIR filters: Algorithms and architectures
L Aksoy, P Flores, J Monteiro
Circuits, Systems, and Signal Processing 33, 1689-1719, 2014
492014
Optimization of combinational and sequential logic circuits for low power using precomputation
J Monteiro, J Rinderknecht, S Devadas, A Ghosh
Proceedings Sixteenth Conference on Advanced Research in VLSI, 430-444, 1995
461995
Implicit FSM decomposition applied to low-power design
JC Monteiro, AL Oliveira
IEEE transactions on very large scale integration (VLSI) systems 10 (5), 560-565, 2002
412002
ระบบไม่สามารถดำเนินการได้ในขณะนี้ โปรดลองใหม่อีกครั้งในภายหลัง
บทความ 1–20