Takip et
Simone Dartizio
Simone Dartizio
Politecnico di Milano
mail.polimi.it üzerinde doğrulanmış e-posta adresine sahip
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 s …
SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...
IEEE Journal of Solid-State Circuits, 2022
272022
4.5 A 9.25 GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
G Castoro, SM Dartizio, F Tesolin, F Buccoleri, M Rossoni, D Cherniak, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 82-84, 2023
252023
4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
SM Dartizio, F Tesolin, G Castoro, F Buccoleri, L Lanzoni, M Rossoni, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 3-5, 2023
242023
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ...
IEEE Journal of Solid-State Circuits, 2021
242021
A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
222022
A Low-Spur and Low-Jitter Fractional- Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
SM Dartizio, F Tesolin, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ...
IEEE Journal of Solid-State Circuits, 2023
202023
A 12.9-to-15.1 GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6 fs Integrated Jitter
M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021
182021
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
M Rossoni, SM Dartizio, F Tesolin, G Castoro, R Dell’Orto, C Samori, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 188-190, 2024
142024
A 72-fs-Total-Integrated-Jitter Two-Core Fractional- Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ...
IEEE Journal of Solid-State Circuits, 2022
122022
32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021
112021
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
F Tesolin, SM Dartizio, F Buccoleri, A Santiccioli, L Bertulessi, C Samori, ...
IEEE Journal of Solid-State Circuits, 2023
82023
A 66.7 fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC
P Salvi, SM Dartizio, M Rossoni, F Tesolin, G Castoro, AL Lacaita, ...
2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024
72024
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Lesurum, ...
2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022
72022
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
F Tesolin, SM Dartizio, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 198-200, 2024
62024
A 59.3 fs Jitter and-62.1 dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector
SM Dartizio, M Rossoni, F Tesolin, G Castoro, C Samori, AL Lacaita, ...
2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024
52024
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators
G Castoro, SM Dartizio, AL Lacaita, S Levantino
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
42022
A Low-Noise Fractional- Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
P Salvi, SM Dartizio, M Rossoni, F Tesolin, G Castoro, AL Lacaita, ...
IEEE Journal of Solid-State Circuits, 2024
12024
A Low-Jitter Fractional- Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
M Rossoni, SM Dartizio, F Tesolin, G Castoro, R Dell’Orto, AL Lacaita, ...
IEEE Journal of Solid-State Circuits, 2024
12024
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
F Tesolin, SM Dartizio, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ...
IEEE Journal of Solid-State Circuits, 2024
12024
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
R Moleri, SM Dartizio, M Rossoni, G Castoro, F Tesolin, D Cherniak, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
12024
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