| Hardware Acceleration of OpenSSL cryptographic functions for high-performance Internet Security M Khalil-Hani, VP Nambiar, MN Marsono 2010 International Conference on Intelligent Systems, Modelling and …, 2010 | 46 | 2010 |
| Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function VP Nambiar, M Khalil-Hani, R Sahnoun, MN Marsono Neurocomputing 140, 228-241, 2014 | 26 | 2014 |
| A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router J Pu, WL Goh, VP Nambiar, MM Wong, AT Do IEEE Transactions on Circuits and Systems I: Regular Papers 68 (12), 5081-5094, 2021 | 24 | 2021 |
| Accelerating the AES encryption function in OpenSSL for embedded systems VP Nambiar, M Khalil-Hani, MM Zabidi International Journal of Information and Communication Technology 2 (1-2), 83-93, 2009 | 22 | 2009 |
| An AES tightly coupled hardware accelerator in an FPGA-based embedded processor core A Irwansyah, VP Nambiar, M Khalil-Hani 2009 International Conference on Computer Engineering and Technology 2, 521-525, 2009 | 21 | 2009 |
| 0.5 V 4.8 pJ/SOP 0.93μW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron VP Nambiar, J Pu, YK Lee, A Mani, T Luo, L Yang, EK Koh, MM Wong, ... 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2020 | 20 | 2020 |
| HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems VP Nambiar, S Balakrishnan, M Khalil-Hani, MN Marsono Computing 95, 863-896, 2013 | 19 | 2013 |
| A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications YS Chong, WL Goh, VP Nambiar, AT Do IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 1662-1666, 2021 | 18 | 2021 |
| A 2.1 pJ/SOP 40nm SNN accelerator featuring on-chip transfer learning using Delta STDP MM Wong, SB Shrestha, VP Nambiar, A Mani, YK Lee, EK Koh, W Jiang, ... ESSDERC 2021-IEEE 51st European Solid-State Device Research Conference …, 2021 | 17 | 2021 |
| Evolvable block-based neural networks for classification of driver drowsiness based on heart rate variability VP Nambiar, M Khalil-Hani, CW Sia, MN Marsono 2012 IEEE International Conference on Circuits and Systems (ICCAS), 156-161, 2012 | 17 | 2012 |
| Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm VP Nambiar, M Khalil-Hani, MN Marsono, CW Sia Neurocomputing 145, 285-302, 2014 | 16 | 2014 |
| Evolvable Block-based Neural Networks for real-time classification of heart arrhythmia From ECG signals VP Nambiar, M Khalil-Hani, MN Marsono 2012 IEEE-EMBS Conference on Biomedical Engineering and Sciences, 866-871, 2012 | 16 | 2012 |
| A low-cost high-throughput digital design of biorealistic spiking neuron J Pu, WL Goh, VP Nambiar, YS Chong, AT Do IEEE Transactions on Circuits and Systems II: Express Briefs 68 (4), 1398-1402, 2020 | 15 | 2020 |
| Block-based spiking neural network hardware with deme genetic algorithm J Pu, VP Nambiar, AT Do, WL Goh 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 14 | 2019 |
| SPICE modelling of a valley switching flyback power supply controller for improved efficiency in low cost devices VP Nambiar, A Yahya, TR Selvaduray 2012 IEEE International Conference on Circuits and Systems (ICCAS), 10-14, 2012 | 12 | 2012 |
| GA-based parameter tuning in finger-vein biometric embedded systems for information security M Khalil-Hani, VP Nambiar, MN Marsono 2012 1st IEEE International Conference on Communications in China (ICCC …, 2012 | 12 | 2012 |
| An MP2 Investigation on the Encapsulation of H2 and 2H2 inside C50 Fullerene A Zeinalinezhad, R Sahnoun, VP Nambiar, M Aziz Chemical Physics Letters, 2014 | 11 | 2014 |
| Efficient implementation of activation functions for lstm accelerators YS Chong, WL Goh, YS Ong, VP Nambiar, AT Do 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021 | 10 | 2021 |
| An energy-efficient convolution unit for depthwise separable convolutional neural networks YS Chong, WL Goh, YS Ong, VP Nambiar, AT Do 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 9 | 2021 |
| A low power and low area router with congestion-aware routing algorithm for spiking neural network hardware implementations J Pu, WL Goh, VP Nambiar, AT Do IEEE Transactions on Circuits and Systems II: Express Briefs 68 (1), 471-475, 2020 | 9 | 2020 |
Anh Tuan DoInstitute of Microelectronicsime.a-star.edu.sg üzerinde doğrulanmış e-posta adresine sahip