Takip et
Arnab Pal
Arnab Pal
UC Santa Barbara
ucsb.edu üzerinde doğrulanmış e-posta adresine sahip
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
2-D layered materials for next-generation electronics: Opportunities and challenges
W Cao, J Jiang, X Xie, A Pal, JH Chu, J Kang, K Banerjee
IEEE Transactions on Electron Devices 65 (10), 4109-4121, 2018
1052018
Quantum‐Engineered Devices Based on 2D Materials for Next‐Generation Information Processing and Storage
A Pal, S Zhang, T Chavan, K Agashiwala, CH Yeh, W Cao, K Banerjee
Advanced Materials 35 (27), 2109894, 2023
672023
One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across Mo S 2/Metal …
K Parto, A Pal, T Chavan, K Agashiwala, CH Yeh, W Cao, K Banerjee
Physical Review Applied 15 (6), 064068, 2021
512021
Analytical drain current modeling of double-gate tunnel field-effect transistors
A Pal, AK Dutta
IEEE Transactions on Electron Devices 63 (8), 3213-3221, 2016
502016
Area-selective-CVD technology enabled top-gated and scalable 2D-heterojunction transistors with dynamically tunable Schottky barrier
CH Yeh, W Cao, A Pal, K Parto, K Banerjee
2019 IEEE International Electron Devices Meeting (IEDM), 23.4. 1-23.4. 4, 2019
282019
Roadmap on printable electronic materials for next-generation sensors
V Pecunia, L Petti, J Andrews, R Ollearo, GH Gelinck, B Nasrollahi, ...
Nano Futures, 2024
192024
Two-dimensional materials enabled next-generation low-energy compute and connectivity
A Pal, K Agashiwala, J Jiang, D Zhang, T Chavan, A Kumar, CH Yeh, ...
MRS Bulletin 46 (12), 1211-1228, 2021
172021
A compact current–voltage model for 2-D-semiconductor-based lateral homo-/hetero-junction tunnel-FETs
A Pal, W Cao, K Banerjee
IEEE Transactions on Electron Devices 67 (10), 4473-4481, 2020
82020
Interfacial thermal conductivity of 2D layered materials: An atomistic approach
K Parto, A Pal, X Xie, W Cao, K Banerjee
2018 IEEE International Electron Devices Meeting (IEDM), 24.1. 1-24.1. 4, 2018
82018
Computational study of gate-induced drain leakage in 2D-semiconductor field-effect transistors
J Kang, W Cao, A Pal, S Pandey, S Kramer, R Hill, G Sandhu, K Banerjee
2017 IEEE International Electron Devices Meeting (IEDM), 31.2. 1-31.2. 4, 2017
82017
An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs
A Pal, Z Chai, J Jiang, W Cao, M Davies, V De, K Banerjee
Nature Communications 15 (1), 3392, 2024
72024
Characterization and closed-form modeling of edge/top/hybrid metal-2D semiconductor contacts
A Pal, V Mishra, J Weber, K Krishnaswamy, K Ghosh, AV Penumatcha, ...
2022 International Electron Devices Meeting (IEDM), 28.5. 1-28.5. 4, 2022
72022
Computational study of spin injection in 2D materials
A Pal, K Parto, K Agashiwala, W Cao, K Banerjee
2019 IEEE International Electron Devices Meeting (IEDM), 24.2. 1-24.2. 4, 2019
32019
Can kinetic inductance in low-dimensional materials enable a new generation of RF-electronics?
K Agashiwala, A Pal, W Cao, J Jiang, K Banerjee
2018 IEEE International Electron Devices Meeting (IEDM), 24.4. 1-24.4. 4, 2018
32018
How to derive the highest mobility from 2D FETs—A first-principle study
A Pal, W Cao, J Kang, K Banerjee
2017 IEEE International Electron Devices Meeting (IEDM), 31.3. 1-31.3. 4, 2017
32017
Strain engineering in 2D FETs: Physics, status, and prospects
A Kumar, L Xu, A Pal, K Agashiwala, K Parto, W Cao, K Banerjee
Journal of Applied Physics 136 (9), 2024
22024
Advancing High-Performance Large-Scale Quantum Computing with Cryogenic 2D-CMOS
K Agashiwala, A Pal, H Cui, T Chavan, W Cao, K Banerjee
2023 International Electron Devices Meeting (IEDM), 1-4, 2023
22023
Three-dimensional transistors with two-dimensional semiconductors for future CMOS scaling
A Pal, T Chavan, J Jabbour, W Cao, K Banerjee
Nature Electronics 7 (12), 1147-1157, 2024
12024
A Framework for Exploring Gate-Dielectric Materials for High-Performance Two-Dimensional Field-Effect-Transistors
A Kumar, L Xu, A Ho, A Pal, K Agashiwala, K Parto, W Cao, K Banerjee
IEEE Transactions on Materials for Electron Devices, 2024
2024
A Materials-Device Co-Design Framework for Realizing Ultra Energy-Efficient All-2D Spin-Logic Circuits with 2D-Materials
S Zhang, A Pal, W Yin, W Cao, K Banerjee, (*equal contribution)
2023 International Electron Devices Meeting (IEDM), 1-4, 2023
2023
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