Avtar Singh

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Katkıda bulunan yazarlar

Saurabh ChaudhuryProfessor, NIT Silcharnits.ac.in üzerinde doğrulanmış e-posta adresine sahip
Dr. Chandan Kumar PandeyAssociate Professor (School of Electronics Engineering), VIT-AP Universityvitap.ac.in üzerinde doğrulanmış e-posta adresine sahip
Manash Chanda, Ph. D (Engg.)Associate Professor and Head, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata 700150ieee.org üzerinde doğrulanmış e-posta adresine sahip
Dr.Rohit LorenzoAssociate Professor, VIT AP Universityvitap.ac.in üzerinde doğrulanmış e-posta adresine sahip
Hemant PardeshiGovernment Polytechnic, Nasikmahaurja.com üzerinde doğrulanmış e-posta adresine sahip
Dr. Sarosij AdakIndependent researcherieee.org üzerinde doğrulanmış e-posta adresine sahip
Inamul HussainIndian Institute of Technology Guwahati, Assam, Indiarnd.iitg.ac.in üzerinde doğrulanmış e-posta adresine sahip
Sudhansu Kumar PatiSilicon Institute of technology, Bhubaneswar, Odishasilicon.ac.in üzerinde doğrulanmış e-posta adresine sahip
Arghyadeep SarkarPostdoc, University of Sherbrookeusherbrooke.ca üzerinde doğrulanmış e-posta adresine sahip
Arun Kumar ChatterjeeAssistant Professor, Thapar Institue of Engineering and Technology, Patialathapar.edu üzerinde doğrulanmış e-posta adresine sahip
Abhigyan GangulyParul University, Indiaparuluniversity.ac.in üzerinde doğrulanmış e-posta adresine sahip
CHANDAN KUMAR SARKARUnknown affiliation ETCE DEPARTMENT Jadavpur University Kolkata 700032 INDIA

Takip et

Avtar Singh

Associate Professor, Adama Science and Technology University,Adama,Ethiopia

ieee.org üzerinde doğrulanmış e-posta adresine sahip

semiconductor devices VLSI MOSFET


Başlık Alıntılara göre sırala Yıla göre sırala Başlığa göre sırala	Alıntı yapanlar Alıntı yapanlar	Yıl
Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances CK Pandey, A Singh, S Chaudhury Applied Physics A 126 (3), 225, 2020	45	2020
Design and analysis of high k silicon nanotube tunnel FET device A Singh, S Chaudhury, C Kumar Pandey, S Madhulika Sharma, ... IET Circuits, Devices & Systems 13 (8), 1305-1310, 2019	38	2019
Ge-source based L-shaped tunnel field effect transistor for low power switching application S Chander, SK Sinha, R Chaudhary, A Singh Silicon, 1-14, 2021	34	2021
Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction A Singh, CK Pandey, U Nanda Microelectronics Journal 126, 105512, 2022	32	2022
Effect of strain in silicon nanotube FET devices for low power applications A Singh, CK Pandey, S Chaudhury, CK Sarkar The European Physical Journal Applied Physics 85 (1), 10101, 2019	30	2019
Evolution and evaluation: Sarcasm analysis for twitter data using sentiment analysis M Bhakuni, K Kumar, Sonia, C Iwendi, A Singh Journal of Sensors 2022 (1), 6287559, 2022	27	2022
A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET CK Pandey, A Singh, S Chaudhury Microelectronics Reliability 122, 114166, 2021	26	2021
Split gated silicon nanotube FET for bio‐sensing applications A Singh, S Chaudhury, M Chanda, CK Sarkar IET Circuits, Devices & Systems 14 (8), 1289-1294, 2020	25	2020
Improved DC performances of gate-all-around si-nanotube tunnel FETs using gate-source overlap A Singh, CK Pandey Silicon 14 (4), 1463-1470, 2022	24	2022
Improved drive capability of silicon nano tube tunnel FET using halo implantation A Singh, S Chaudhary, SM Sharma, CK Sarkar Silicon 12 (11), 2555-2561, 2020	23	2020
Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage S Adak, SK Swain, A Singh, H Pardeshi, SK Pati, CK Sarkar Physica E: Low-dimensional Systems and Nanostructures 64, 152-157, 2014	21	2014
Tuning of threshold voltage in silicon nano-tube FET using halo doping and its impact on analog/RF performances A Singh, CK Pandey, S Chaudhury, CK Sarkar Silicon 13 (11), 3871-3877, 2021	18	2021
A review on the effects of technology on CMOS and CPL logic style on performance, speed and power dissipation I Hussain, A Singh, S Chaudhury 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 332-336, 2018	12	2018
A review on the compact modeling of parasitic capacitance: from basic to advanced FETs SM Sharma, A Singh, S Dasgupta, MV Kartikeyan Journal of Computational Electronics 19 (3), 1116-1125, 2020	11	2020
Comparative assesment of ground plane and strained based FDSOI MOSFET A Singh, S Adak, H Pardeshi, A Sarkar, CK Sarkar Informacije MIDEM 45 (1), 73-79, 2015	11	2015
Analysis of interface trap charges on dielectric pocket soi-tfet CK Pandey, A Singh, S Chaudhury 2019 Devices for Integrated Circuit (DevIC), 337-340, 2019	9	2019
Nanoscale devices: physics, modeling, and their application BK Kaushik CRC Press, 2018	8	2018
Diving into progress: a review on current therapeutic advancements in spinal muscular atrophy P Bagga, S Singh, G Ram, S Kapil, A Singh Frontiers in Neurology 15, 1368658, 2024	6	2024
Assessment of Hetero-Structure Junction-Less Tunnel FET’s Efficacy for Biosensing Applications R Abdulnassir, A Singh, D Tekilu, G Subarao, M Chanda Sensing and Imaging 25 (1), 6, 2023	6	2023
Silicon Nanotube Tunnel FET as a Label Free Biosensor. A Singh, AF Shifaw, D Tekilu, M Chanda International Journal of Nanoelectronics & Materials 14 (3), 2021	5	2021

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