Takip et
Steve Dai
Steve Dai
NVIDIA Research
nvidia.com üzerinde doğrulanmış e-posta adresine sahip - Ana Sayfa
Başlık
Alıntı yapanlar
Alıntı yapanlar
Yıl
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs
Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
1612018
Magnet: A modular accelerator generator for neural networks
R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
1412019
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
S Dai, Y Zhou, H Zhang, E Ustun, EFY Young, Z Zhang
2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018
1362018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
1342018
Accelerating chip design with machine learning
B Khailany
Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 33-33, 2020
862020
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
JR Stevens, R Venkatesan, S Dai, B Khailany, A Raghunathan
2021 58th ACM/IEEE Design Automation Conference (DAC), 469-474, 2021
842021
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
S Dai, R Venkatesan, H Ren, B Zimmer, WJ Dally, B Khailany
arXiv preprint arXiv:2102.04503, 2021
702021
Elasticflow: A complexity-effective approach for pipelining irregular loop nests
M Tan, G Liu, R Zhao, S Dai, Z Zhang
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 78-85, 2015
632015
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
432017
Flushing-enabled loop pipelining for high-level synthesis
S Dai, M Tan, K Hao, Z Zhang
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
412014
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training
C Sakr, S Dai, R Venkatesan, B Zimmer, W Dally, B Khailany
International Conference on Machine Learning, 19123-19138, 2022
402022
Multithreaded pipeline synthesis for data-parallel kernels
M Tan, B Liu, S Dai, Z Zhang
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 718-725, 2014
402014
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
382017
A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
2019 Symposium on VLSI Circuits, C30-C31, 2019
352019
High-level synthesis for low-power design
Z Zhang, D Chen, S Dai, K Campbell
IPSJ Transactions on System and LSI Design Methodology 8, 12-25, 2015
342015
Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
332019
A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm
B Keller, R Venkatesan, S Dai, SG Tell, B Zimmer, WJ Dally, CT Gray, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
312022
High-Level Synthesis with Timing-Sensitive Information Flow Enforcement
Z Jiang, S Dai, GE Suh, Z Zhang
International Conference On Computer Aided Design (ICCAD), 2018
302018
Area-efficient pipelining for FPGA-targeted high-level synthesis
R Zhao, M Tan, S Dai, Z Zhang
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
302015
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
B Keller, R Venkatesan, S Dai, SG Tell, B Zimmer, C Sakr, WJ Dally, ...
IEEE Journal of Solid-State Circuits 58 (4), 1129-1141, 2023
292023
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