| A hardware perspective on the ChaCha ciphers: Scalable Chacha8/12/20 implementations ranging from 476 slices to bitrates of 175 Gbit/s J Pfau, M Reuter, T Harbaum, K Hofmann, J Becker 2019 32nd IEEE International System-on-Chip Conference (SOCC), 294-299, 2019 | 21 | 2019 |
| From mosfets to ambipolar transistors: Standard cell synthesis for the planar rfet technology M Reuter, J Pfau, TA Krauss, J Becker, K Hofmann IEEE Transactions on Circuits and Systems I: Regular Papers 68 (1), 114-125, 2020 | 19 | 2020 |
| Towards ambipolar planar devices: The DeFET device in area constrained XOR applications M Reuter, J Pfau, TA Krauss, M Moradinasab, U Schwalke, J Becker, ... 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020 | 7 | 2020 |
| From MOSFETs to ambipolar transistors: A static DeFET inverter cell for SOI M Reuter, TA Krauss, M Moradinasab, J Pfau, U Schwalke, J Becker, ... 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 113-116, 2019 | 7 | 2019 |
| Machine Learning Based Compact Model Design for Reconfigurable FETs M Reuter, J Wilm, A Kramer, N Bhattacharjee, C Beyer, J Trommer, ... IEEE Journal of the Electron Devices Society, 2024 | 5 | 2024 |
| Reconfiguring an RFET Based Differential Amplifier M Reuter, A Kramer, T Krauss, J Pfau, J Becker, K Hofmann 2022 IEEE 40th Central America and Panama Convention (CONCAPAN), 1-6, 2022 | 5 | 2022 |
| Single Transistor Analog Building Blocks: Exploiting Back-Bias Reconfigurable Devices N Bhattacharjee, M Reuter, K Hofmann, T Mikolajick, J Trommer 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5, 2023 | 4 | 2023 |
| Quick Compact Model Development Through Slow Transient Simulation: An Alternative Approach to Table Models for Emerging Nanodevices M Reuter, D Lee, D Riehl, K Hofmann 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 485-489, 2022 | 3 | 2022 |
| Generating Predictive Models for Emerging Semiconductor Devices M Reuter, A Kramer, D Lee, J Trommer, N Bhattacharjee, G Galderisi, ... IEEE Journal of the Electron Devices Society, 2023 | 2 | 2023 |
| Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design J Pfau, J Hernandez, M Reuter, K Hofmann, J Becker 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 1-7, 2023 | 1 | 2023 |
| Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology J Pfau, M Reuter, K Hofmann, J Becker 2020 International Conference on Field-Programmable Technology (ICFPT), 165-173, 2020 | 1 | 2020 |
| Speeding-Up Emerging Device Development Cycles by Generating Models via Machine-Learning directly from Electrical Measurements J Trommer, M Reuter, N Bhattacharjee, Y He, V Sessi, M Drescher, M Zier, ... 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 217-220, 2024 | | 2024 |
| Data Driven Compact Modeling of a Reconfigurable FET MJ Reuter Technische Universität Darmstadt, 0 | | |
