| A 4096‐neuron 1M‐synapse 3.8pJ/SOP Spiking Neural Network with On‐chip STDP Learning and Sparse Weights in 10nm FinFET CMOS GK Chen, R Kumar, HE Sumbul, P Knag, RK Krishnamurthy IEEE VLSI Circuits, 2018, 2018 | 233 | 2018 |
| Building trusted ICs using split fabrication K Vaidyanathan, BP Das, HE Sumbul, R Liu, L Pileggi Hardware-Oriented Security and Trust (HOST), 2014 | 156* | 2014 |
| A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing Q Zhu, B Akin, HE Sumbul, F Sadi, JC Hoe, L Pileggi, F Franchetti 2013 IEEE international 3D systems integration conference (3DIC), 1-7, 2013 | 153 | 2013 |
| Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware Q Zhu, T Graf, HE Sumbul, L Pileggi, F Franchetti 2013 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2013 | 140 | 2013 |
| Compute in memory circuits with multi-Vdd arrays and/or analog multipliers HE Sumbul, P Knag, GK Chen, R Kumar, A Sharma, S Manipatruni, ... US Patent 11,061,646, 2021 | 85 | 2021 |
| Efficient and Secure Intellectual Property (IP) Design with Split Fabrication K Vaidyanathan, R Liu, HE Sumbul, Q Zhu, F Franchetti, L Pileggi Hardware-Oriented Security and Trust (HOST), 2014 | 85 | 2014 |
| Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs E Nurvitadhi, D Kwon, A Jafari, A Boutros, J Sim, P Tomson, H Sumbul, ... 27th IEEE International Symposium On Field-Programmable Custom Computing …, 2019 | 75 | 2019 |
| A 617TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS PC Knag, GK Chen, HE Sumbul, R Kumar, MA Anders, H Kaul, SK Hsu, ... 2020 Symposia on VLSI Technology and Circuits, 2020 | 62 | 2020 |
| Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits A Sharma, JT Kavalieros, IA Young, S Manipatruni, R Krishnamurthy, ... US Patent 11,138,499, 2021 | 59 | 2021 |
| In-memory multiply and accumulate with global charge-sharing HE Sumbul, GK Chen, R Kumar, P Knag, A Sharma, S Manipatruni, ... US Patent 10,748,603, 2020 | 41 | 2020 |
| Binary, ternary and bit serial compute-in-memory circuits P Knag, GK Chen, R Kumar, HE Sumbul, A Sharma, S Manipatruni, ... US Patent 10,642,922, 2020 | 38 | 2020 |
| Compute in memory circuits with time-to-digital computation R Kumar, P Knag, GK Chen, HE Sumbul, S Manipatruni, A Mathuriya, ... US Patent 11,048,434, 2021 | 35 | 2021 |
| Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks D Przewlocka-Rus, SS Sarwar, HE Sumbul, Y Li, BD Salvo tinyML Research Symposium, 2022 | 34 | 2022 |
| Neuromorphic computer with reconfigurable memory mapping for various neural network topologies GK Chen, R Kumar, HE Sumbul, P Knag, RK Krishnamurthy US Patent 11,062,203, 2021 | 34 | 2021 |
| System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars HE Sumbul, TF Wu, Y Li, SS Sarwar, W Koven, E Murphy-Trotzky, X Cai, ... IEEE Custom Integrated Circuits Conference (CICC), 2022 | 33 | 2022 |
| Compute near memory convolution accelerator HE Sumbul, GK Chen, P Knag, R Kumar, R Krishnamurthy US Patent 11,726,950, 2023 | 31 | 2023 |
| Reconfigurable memory compression techniques for deep neural networks R Kumar, GK Chen, HE Sumbul, P Knag, R Krishnamurthy US Patent 11,625,584, 2023 | 29 | 2023 |
| Programmable interface to in-memory cache processor A Mathuriya, S Manipatruni, V Lee, H Sumbul, G Chen, R Kumar, P Knag, ... US Patent 10,705,967, 2020 | 27 | 2020 |
| Digital bit-serial multi-multiply-and-accumulate compute in memory GK Chen, R Kumar, HE Sumbul, P Knag, R Krishnamurthy, S Manipatruni, ... US Patent 10,831,446, 2020 | 24 | 2020 |
| Techniques for current-sensing circuit design for compute-in-memory GK Chen, R Kumar, HE Sumbul, P Knag, R Krishnamurthy, S Manipatruni, ... US Patent 10,877,752, 2020 | 24 | 2020 |
Raghavan KumarIntel LabsПідтверджена електронна адреса в intel.com