| Dynamic power consumption in Virtex™-II FPGA family L Shang, AS Kaviani, K Bathala Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002 | 544 | 2002 |
| Computational field programmable architecture AS Kaviani, SD Brown US Patent 6,140,839, 2000 | 224 | 2000 |
| Hybrid FPGA architecture A Kaviani, S Brown Proceedings of the 1996 ACM fourth international symposium on Field …, 1996 | 170 | 1996 |
| Rapidwright: Enabling custom crafted implementations for fpgas C Lavin, A Kaviani 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 139 | 2018 |
| Computational field programmable architecture A Kaviani, D Vranesic, S Brown Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No …, 1998 | 132 | 1998 |
| Integrated circuit and method of asynchronously routing data in an integrated circuit AS Kaviani US Patent 8,294,490, 2012 | 59 | 2012 |
| The hybrid field-programmable architecture A Kaviani, S Brown IEEE Design & Test of Computers 16 (2), 74-83, 1999 | 48 | 1999 |
| RapidStream: Parallel physical implementation of FPGA HLS designs L Guo, P Maidee, Y Zhou, C Lavin, J Wang, Y Chi, W Qiao, A Kaviani, ... Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 47 | 2022 |
| Counter-controlled delay line AS Kaviani US Patent 7,071,751, 2006 | 32 | 2006 |
| Configurable logic block for PLD with logic gate for combining output with another configurable logic block AS Kaviani, S Mohan, RD Wittig, SP Young, BJ New US Patent 6,603,332, 2003 | 32 | 2003 |
| FPGA with improved structure for implementing large multiplexers AS Kaviani US Patent 6,556,042, 2003 | 27 | 2003 |
| Boolean satisfiability-based routing and its application to xilinx ultrascale clock network H Fraisse, A Joshi, D Gaitonde, A Kaviani Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 26 | 2016 |
| Structure for reducing leakage current in submicron IC devices AS Kaviani US Patent 6,914,449, 2005 | 26 | 2005 |
| RWRoute: An open-source timing-driven router for commercial FPGAs Y Zhou, P Maidee, C Lavin, A Kaviani, D Stroobandt ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15 (1), 1-27, 2021 | 24 | 2021 |
| Technology mapping issues for an FPGA with lookup tables and PLA-like blocks A Kaviani, S Brown Proceedings of the 2000 ACM/SIGDA eighth international symposium on field …, 2000 | 23 | 2000 |
| Implementing wide multiplexers in an FPGA using a horizontal chain structure AS Kaviani US Patent 6,466,052, 2002 | 22 | 2002 |
| Hybrid programmable logic device AS Kaviani US Patent 5,841,295, 1998 | 19 | 1998 |
| Method for implementing a programmable logic device having look-up table and product-term circuitry AS Kaviani US Patent 6,212,670, 2001 | 17 | 2001 |
| An open-source lightweight timing model for RapidWright P Maidee, C Neely, A Kaviani, C Lavin 2019 International Conference on Field-Programmable Technology (ICFPT), 171-178, 2019 | 14 | 2019 |
| Analyzing the divide between FPGA academic and commercial results E Vansteenkiste, A Kaviani, H Fraisse 2015 International Conference on Field Programmable Technology (FPT), 96-103, 2015 | 14 | 2015 |
