| Training neural network for machine intelligence in automatic test pattern generator S Roy, SK Millican, VD Agrawal 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 30 | 2021 |
| Machine intelligence for efficient test pattern generation S Roy, SK Millican, VD Agrawal 2020 IEEE International Test Conference (ITC), 1-5, 2020 | 30 | 2020 |
| Test point insertion using artificial neural networks Y Sun, S Millican 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 253-258, 2019 | 29 | 2019 |
| Applying neural networks to delay fault testing: Test point insertion and random circuit training S Millican, Y Sun, S Roy, V Agrawal 2019 IEEE 28th Asian Test Symposium (ATS), 13-135, 2019 | 28 | 2019 |
| Special session–machine learning in test: A survey of analog, digital, memory, and rf integrated circuits S Roy, SK Millican, VD Agrawal 2021 IEEE 39th VLSI Test Symposium (VTS), 1-14, 2021 | 27 | 2021 |
| Improved random pattern delay fault coverage using inversion test points S Roy, B Stiene, SK Millican, VD Agrawal 2019 IEEE 28th North Atlantic Test Workshop (NATW), 206-211, 2019 | 25 | 2019 |
| Linear programming formulations for thermal-aware test scheduling of 3D-stacked integrated circuits SK Millican, KK Saluja 2012 IEEE 21st Asian Test Symposium, 37-42, 2012 | 24 | 2012 |
| Principal component analysis in machine intelligence-based test generation S Roy, SK Millican, VD Agrawal 2021 IEEE Microelectronics Design & Test Symposium (MDTS), 1-6, 2021 | 20 | 2021 |
| Special session: Delay fault testing-present and future J Mahmod, S Millican, U Guin, V Agrawal 2019 IEEE 37th VLSI Test Symposium (VTS), 1-10, 2019 | 20 | 2019 |
| Unsupervised learning in test generation for digital integrated circuits S Roy, SK Millican, VD Agrawal 2021 IEEE European Test Symposium (ETS), 1-4, 2021 | 14 | 2021 |
| Improved pseudo-random fault coverage through inversions: a study on test point architectures S Roy, B Stiene, SK Millican, VD Agrawal Journal of Electronic Testing 36, 123-133, 2020 | 14 | 2020 |
| A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits SK Millican, KK Saluja 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 14 | 2014 |
| Formulating optimal test scheduling problem with dynamic voltage and frequency scaling SK Millican, KK Saluja 2013 22nd Asian Test Symposium, 165-170, 2013 | 13 | 2013 |
| Special session: Survey of test point insertion for logic built-in self-test Y Sun, SK Millican, VD Agrawal 2020 IEEE 38th VLSI Test Symposium (VTS), 1-6, 2020 | 11 | 2020 |
| Multi-heuristic machine intelligence guidance in automatic test pattern generation S Roy, SK Millican, VD Agrawal 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS), 1-6, 2022 | 9 | 2022 |
| Calculating signal controllability using neural networks: Improvements to testability analysis and test point insertion J Immanuel, SK Millican 2020 IEEE 29th North Atlantic Test Workshop (NATW), 1-6, 2020 | 9 | 2020 |
| System and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuits S Millican, Y Sun, S Roy, VD Agrawal US Patent App. 17/226,950, 2021 | 7 | 2021 |
| Optimal test scheduling of stacked circuits under various hardware and power constraints SK Millican, KK Saluja 2015 28th International Conference on VLSI Design, 487-492, 2015 | 7 | 2015 |
| Applying artificial neural networks to logic built-in self-test: Improving test point insertion Y Sun, SK Millican Journal of Electronic Testing 38 (4), 339-352, 2022 | 6 | 2022 |
| Optimal test scheduling formulation under power constraints with dynamic voltage and frequency scaling SK Millican, KK Saluja Journal of Electronic Testing 30, 569-580, 2014 | 5 | 2014 |
