| Copper plating for 3D interconnects A Radisic, O Lühn, HGG Philipsen, Z El-Mekki, M Honore, S Rodet, ... Microelectronic Engineering 88 (5), 701-704, 2011 | 101 | 2011 |
| Anisotropy in the wet-etching of semiconductors JJ Kelly, HGG Philipsen Current opinion in solid state and materials science 9 (1-2), 84-90, 2005 | 74 | 2005 |
| Large area copper plated silicon solar cell exceeding 19.5 % efficiency L Tous, R Russell, J Das, R Labie, M Ngamo, J Horzel, H Philipsen, ... Energy Procedia 21, 58-65, 2012 | 71 | 2012 |
| Scalable through silicon via with polymer deep trench isolation for 3D wafer level packaging DS Tezcan, F Duval, H Philipsen, O Luhn, P Soussan, B Swinnen 59th Electronic Components and Technology Conference, 1159-1164, 2009 | 71 | 2009 |
| Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias F Inoue, H Philipsen, A Radisic, S Armini, Y Civale, P Leunissen, ... Electrochimica Acta 100, 203-211, 2013 | 66 | 2013 |
| Impact of post-plating anneal and through-silicon via dimensions on Cu pumping J De Messemaeker, OV Pedreira, B Vandevelde, H Philipsen, I De Wolf, ... 2013 IEEE 63rd Electronic Components and Technology Conference, 586-591, 2013 | 65 | 2013 |
| Correlation between Cu microstructure and TSV Cu pumping J De Messemaeker, OV Pedreira, H Philipsen, E Beyne, I De Wolf, ... Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th, 613 …, 2014 | 63 | 2014 |
| Implementation of an industry compliant, 5 × 50 μm, via-middle TSV technology on 300 mm wafers A Redolfi, D Velenis, S Thangaraju, P Nolmans, P Jaenen, M Kostermans, ... Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 1384 …, 2011 | 60 | 2011 |
| 3-D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias Y Civale, DS Tezcan, HGG Philipsen, FFC Duval, P Jaenen, Y Travaly, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (6 …, 2011 | 59 | 2011 |
| A simple copper metallisation process for high cell efficiencies and reliable modules R Russell, L Tous, H Philipsen, J Horzel, E Cornagliotti, M Ngamo Toko, ... 27th European Photovoltaic Solar Energy Conference and Exhibition - EUPVSEC, 2012 | 58 | 2012 |
| Void-free filling of HAR TSVs using a wet alkaline Cu seed on CVD Co as a replacement for PVD Cu seed S Armini, Z El-Mekki, K Vandersmissen, H Philipsen, S Rodet, M Honore, ... Journal of The Electrochemical Society 158 (2), H160, 2010 | 50 | 2010 |
| Anisotropy in the anodic oxidation of silicon in KOH solution HGG Philipsen, JJ Kelly The Journal of Physical Chemistry B 109 (36), 17245-17253, 2005 | 47 | 2005 |
| High efficiency silver-free heterojunction silicon solar cell JL Hernandez, K Yoshikawa, A Feltrin, N Menou, N Valckx, E Van Assche, ... Japanese Journal of Applied Physics 51 (10S), 10NA04, 2012 | 38 | 2012 |
| Electroless copper bath stability monitoring with UV-Vis spectroscopy, pH, and mixed potential measurements F Inoue, H Philipsen, A Radisic, S Armini, Y Civale, S Shingubara, ... Journal of The Electrochemical Society 159 (7), D437, 2012 | 38 | 2012 |
| High frequency scanning acoustic microscopy applied to 3D integrated process: void detection in through silicon vias A Phommahaxay, I De Wolf, P Hoffrogge, S Brand, P Czurratis, ... 2013 IEEE 63rd Electronic Components and Technology Conference, 227-231, 2013 | 33 | 2013 |
| Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects Y Civale, S Armini, H Philipsen, A Redolfi, D Velenis, K Croes, N Heylen, ... 2012 IEEE 62nd electronic components and technology conference, 822-826, 2012 | 32 | 2012 |
| Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping Y Civale, DS Tezcan, HGG Philipsen, P Jaenen, R Agarwal, F Duval, ... 2009 IEEE International Conference on 3D System Integration, 1-4, 2009 | 28 | 2009 |
| Impact of thinning and through silicon via proximity on high-k/metal gate first CMOS performance A Mercha, A Redolfi, M Stucchi, N Minas, J Van Olmen, S Thangaraju, ... 2010 Symposium on VLSI Technology, 109-110, 2010 | 27 | 2010 |
| Co-W nanocrystalline electrodeposits as barrier for interconnects N Tsyntsaru, G Kaziukaitis, C Yang, H Cesiulis, HGG Philipsen, M Lelis, ... Journal of Solid State Electrochemistry 18, 3057-3064, 2014 | 24 | 2014 |
| Influence of chemical additives on the surface reactivity of Si in KOH solution HGG Philipsen, JJ Kelly Electrochimica Acta 54 (13), 3526-3531, 2009 | 20 | 2009 |
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